diff --git a/components/esp32/sleep_modes.c b/components/esp32/sleep_modes.c
index 090c9a7b83..574ccc079c 100644
--- a/components/esp32/sleep_modes.c
+++ b/components/esp32/sleep_modes.c
@@ -714,10 +714,6 @@ static uint32_t get_power_down_flags(void)
 
 void esp_deep_sleep_disable_rom_logging(void)
 {
-    /* To disable logging in the ROM, only the least significant bit of the register is used,
-     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
-     * you need to write to this register in the same format.
-     * Namely, the upper 16 bits and lower should be the same.
-     */
-    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+    esp_rom_disable_logging();
 }
+
diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index 43c2578bb4..930dcd53d2 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -1,6 +1,8 @@
 idf_build_get_property(target IDF_TARGET)
 
-idf_component_register(SRCS "patches/esp_rom_crc.c" "patches/esp_rom_sys.c" "patches/esp_rom_uart.c"
+idf_component_register(SRCS "patches/esp_rom_crc.c" 
+                            "patches/esp_rom_sys.c" 
+                            "patches/esp_rom_uart.c" 
                        INCLUDE_DIRS include
                        PRIV_INCLUDE_DIRS "${target}"
                        PRIV_REQUIRES soc)
@@ -82,7 +84,6 @@ else() # Regular app build
     endif()
 
     target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}")
-
 endif()
 
 if(target STREQUAL "esp32s2")
diff --git a/components/esp_rom/component.mk b/components/esp_rom/component.mk
index e4bebe71a6..f83357ffec 100644
--- a/components/esp_rom/component.mk
+++ b/components/esp_rom/component.mk
@@ -1,5 +1,5 @@
 COMPONENT_ADD_INCLUDEDIRS := include
-COMPONENT_SRCDIRS := patches
+COMPONENT_SRCDIRS := patches .
 COMPONENT_PRIV_INCLUDEDIRS := esp32
 
 #Linker scripts used to link the final application.
diff --git a/components/esp_rom/include/esp32s2/rom/rtc.h b/components/esp_rom/include/esp32s2/rom/rtc.h
index 593e885457..c91916fa35 100644
--- a/components/esp_rom/include/esp32s2/rom/rtc.h
+++ b/components/esp_rom/include/esp32s2/rom/rtc.h
@@ -71,7 +71,6 @@ extern "C" {
 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
 
-
 typedef enum {
     AWAKE = 0,             //<CPU ON
     LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
diff --git a/components/esp_rom/include/esp_rom_sys.h b/components/esp_rom/include/esp_rom_sys.h
index a4df91b931..68a538b1b7 100644
--- a/components/esp_rom/include/esp_rom_sys.h
+++ b/components/esp_rom/include/esp_rom_sys.h
@@ -46,6 +46,11 @@ void esp_rom_delay_us(uint32_t us);
  */
 void esp_rom_install_channel_putc(int channel, void (*putc)(char c));
 
+/**
+ *  @brief Disable logging from the ROM code.
+ */
+void esp_rom_disable_logging(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c
index b0c47057b7..9495ec743b 100644
--- a/components/esp_rom/patches/esp_rom_sys.c
+++ b/components/esp_rom/patches/esp_rom_sys.c
@@ -15,6 +15,14 @@
 #include <stdint.h>
 #include "esp_attr.h"
 
+#include "sdkconfig.h"
+
+#ifdef CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/rtc.h"
+#endif
+
 IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
 {
     extern void ets_install_putc1(void (*p)(char c));
@@ -30,3 +38,15 @@ IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
         break;
     }
 }
+
+void esp_rom_disable_logging(void)
+{
+#if CONFIG_IDF_TARGET_ESP32 // [refactor-todo]: ESP32S2 seem to also reference disabling logging in its ROM code
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+#endif
+}