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Merge branch 'ci/enable_hello_world_build_on_esp32c5' into 'master'

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ci(esp32c5): enable template app & hello world build on ci

See merge request espressif/esp-idf!28776
This commit is contained in:
Kevin (Lao Kaiyao) 2024-02-05 18:25:37 +08:00
commit 1458e13b50
14 changed files with 87 additions and 35 deletions
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3
.gitlab/ci/default-build-test-rules.yml
View File

@ -9,7 +9,8 @@
extra_default_build_targets:
- esp32p4
# bypass_check_test_targets:
bypass_check_test_targets:
- esp32c5
# - esp32p4
#
# These lines would

3
components/esp_driver_ledc/linker.lf
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@ -9,4 +9,5 @@ entries:
[mapping:ledc_hal]
archive: libhal.a
entries:
ledc_hal_iram (noflash)
if SOC_LEDC_SUPPORTED = y:
ledc_hal_iram (noflash)

29
components/esp_hw_support/include/esp_private/esp_pmu.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -13,13 +13,26 @@
#include "soc/soc_caps.h"
#if SOC_PMU_SUPPORTED
#include "hal/pmu_hal.h"
#include "pmu_param.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief PMU ICG modem code of HP system
* @note This type is required in rtc_clk_init.c when PMU not fully supported
*/
typedef enum {
PMU_HP_ICG_MODEM_CODE_SLEEP = 0,
PMU_HP_ICG_MODEM_CODE_MODEM = 1,
PMU_HP_ICG_MODEM_CODE_ACTIVE = 2,
} pmu_hp_icg_modem_mode_t;
#if SOC_PMU_SUPPORTED
#include "hal/pmu_hal.h"
#include "pmu_param.h"
#define RTC_SLEEP_PD_DIG PMU_SLEEP_PD_TOP //!< Deep sleep (power down digital domain, includes all power domains
// except CPU, Modem, LP peripheral, AON，VDDSDIO, MEM and clock power domains)
@ -173,16 +186,6 @@ typedef enum pmu_sleep_regdma_entry {
PMU_SLEEP_REGDMA_ENTRY_MAX
} pmu_sleep_regdma_entry_t;
/**
* @brief PMU ICG modem code of HP system
*/
typedef enum {
PMU_HP_ICG_MODEM_CODE_SLEEP = 0,
PMU_HP_ICG_MODEM_CODE_MODEM = 1,
PMU_HP_ICG_MODEM_CODE_ACTIVE = 2,
} pmu_hp_icg_modem_mode_t;
/**
* @brief Enable_regdma_backup.
*/

2
components/esp_hw_support/linker.lf
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@ -18,7 +18,7 @@ entries:
if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED = y:
rtc_init:rtc_vddsdio_get_config (noflash)
rtc_init:rtc_vddsdio_set_config (noflash)
if IDF_TARGET_ESP32C6 = n && IDF_TARGET_ESP32H2 = n && IDF_TARGET_ESP32P4 = n: # TODO: IDF-5645
if SOC_PMU_SUPPORTED = n:
rtc_sleep (noflash_text)
rtc_time (noflash_text)
if SOC_PMU_SUPPORTED = y:

6
components/esp_hw_support/port/esp32c5/CMakeLists.txt
View File

@ -6,6 +6,12 @@ set(srcs "rtc_clk_init.c"
"chip_info.c"
)
# TODO: [ESP32C5] IDF-8667
if(IDF_TARGET STREQUAL "esp32c5")
list(REMOVE_ITEM srcs "pmu_init.c"
"pmu_param.c")
endif()
if(NOT BOOTLOADER_BUILD)
list(APPEND srcs "sar_periph_ctrl.c"
"esp_crypto_lock.c")

6
components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
View File

@ -10,10 +10,8 @@
#include <stdlib.h>
#include <esp_types.h>
#include "soc/soc_caps.h"
#if SOC_PMU_SUPPORTED
#include "soc/pmu_struct.h"
#include "hal/pmu_hal.h"
#endif
// TODO: [ESP32C5] IDF-8643
@ -25,8 +23,6 @@ extern "C" {
#define HP_CALI_DBIAS 25
#define LP_CALI_DBIAS 26
#if SOC_PMU_SUPPORTED
// FOR XTAL FORCE PU IN SLEEP
#define PMU_PD_CUR_SLEEP_ON 0
#define PMU_BIASSLP_SLEEP_ON 0
@ -474,8 +470,6 @@ typedef struct pmu_sleep_machine_constant {
} \
}
#endif // SOC_PMU_SUPPORTED
#ifdef __cplusplus
}
#endif

1
components/esp_hw_support/port/esp32c5/rtc_clk_init.c
View File

@ -23,7 +23,6 @@
#include "hal/clk_tree_ll.h"
#include "hal/modem_syscon_ll.h"
#include "hal/modem_lpcon_ll.h"
#include "soc/pmu_reg.h"
#include "pmu_param.h"
static const char *TAG = "rtc_clk_init";

4
components/esp_system/port/soc/esp32c5/cache_err_int.c
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@ -57,8 +57,8 @@ void esp_cache_err_int_init(void)
esp_rom_route_intr_matrix(core_id, ETS_CACHE_INTR_SOURCE, ETS_CACHEERR_INUM);
/* Set the type and priority to cache error interrupts. */
esprv_intc_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
esprv_int_set_type(ETS_CACHEERR_INUM, INTR_TYPE_LEVEL);
esprv_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
/* On the hardware side, start by clearing all the bits reponsible for cache access error */

52
components/hal/esp32c5/include/hal/crosscore_int_ll.h Normal file
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@ -0,0 +1,52 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "esp_attr.h"
#include "soc/intpri_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Clear the crosscore interrupt that just occurred on the current core
*/
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
{
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, 0);
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
*/
FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
{
WRITE_PERI_REG(INTPRI_CPU_INTR_FROM_CPU_0_REG, INTPRI_CPU_INTR_FROM_CPU_0);
}
/**
* @brief Get the state of the crosscore interrupt register for the given core
*
* @param core_id Core to get the crosscore interrupt state of. Ignored on single core targets.
*
* @return Non zero value if a software interrupt is pending on the given core,
* 0 if no software interrupt is pending.
*/
FORCE_INLINE_ATTR uint32_t crosscore_int_ll_get_state(int core_id)
{
return REG_READ(INTPRI_CPU_INTR_FROM_CPU_0_REG);
}
#ifdef __cplusplus
}
#endif

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@ -31,10 +31,6 @@ config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_PMU_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED
bool
default y

2
components/soc/esp32c5/include/soc/soc_caps.h
View File

@ -56,7 +56,7 @@
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638, IDF-8640

2
examples/get-started/.build-test-rules.yml
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@ -8,4 +8,4 @@ examples/get-started/blink:
examples/get-started/hello_world:
enable:
- if: INCLUDE_DEFAULT == 1 or IDF_TARGET == "linux"
- if: INCLUDE_DEFAULT == 1 or IDF_TARGET in ["linux", "esp32c5"]

4
examples/get-started/hello_world/README.md
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@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | ----- |
# Hello World Example

4
tools/ci/build_template_app.sh
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@ -62,7 +62,7 @@ build_stage2() {
--size-file size.json \
--keep-going \
--collect-size-info size_info.txt \
--default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c6 esp32h2 esp32p4
--default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4
}
build_stage1() {
@ -76,7 +76,7 @@ build_stage1() {
--build-log ${BUILD_LOG_CMAKE} \
--size-file size.json \
--collect-size-info size_info.txt \
--default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c6 esp32h2 esp32p4
--default-build-targets esp32 esp32s2 esp32s3 esp32c2 esp32c3 esp32c5 esp32c6 esp32h2 esp32p4
}
# Default arguments