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Merge branch 'refactor/vfs_uart_multichip_support' into 'master'

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vfs_uart & uart: add multichip support

See merge request idf/esp-idf!5298
This commit is contained in:
Angus Gratton 2019-06-20 18:31:24 +08:00
commit 126b687c75
10 changed files with 182 additions and 107 deletions
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12
components/driver/include/driver/uart.h
View File

@ -1,9 +1,9 @@
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
@ -12,15 +12,14 @@
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _DRIVER_UART_H_
#define _DRIVER_UART_H_
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include "soc/uart_periph.h"
#include "soc/uart_caps.h"
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "driver/periph_ctrl.h"
@ -82,7 +81,9 @@ typedef enum {
typedef enum {
UART_NUM_0 = 0x0, /*!< UART base address 0x3ff40000*/
UART_NUM_1 = 0x1, /*!< UART base address 0x3ff50000*/
#if SOC_UART_NUM > 2
UART_NUM_2 = 0x2, /*!< UART base address 0x3ff6e000*/
#endif
UART_NUM_MAX,
} uart_port_t;
@ -844,4 +845,3 @@ esp_err_t uart_get_wakeup_threshold(uart_port_t uart_num, int* out_wakeup_thresh
}
#endif
#endif /*_DRIVER_UART_H_*/

26
components/driver/uart.c
View File

@ -29,6 +29,8 @@
#include "driver/gpio.h"
#include "driver/uart_select.h"
#define UART_NUM SOC_UART_NUM
#define XOFF (char)0x13
#define XON (char)0x11
@ -113,8 +115,20 @@ typedef struct {
static uart_obj_t *p_uart_obj[UART_NUM_MAX] = {0};
/* DRAM_ATTR is required to avoid UART array placed in flash, due to accessed from ISR */
static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = {&UART0, &UART1, &UART2};
static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED};
static DRAM_ATTR uart_dev_t* const UART[UART_NUM_MAX] = {
&UART0,
&UART1,
#if UART_NUM > 2
&UART2
#endif
};
static portMUX_TYPE uart_spinlock[UART_NUM_MAX] = {
portMUX_INITIALIZER_UNLOCKED,
portMUX_INITIALIZER_UNLOCKED,
#if UART_NUM > 2
portMUX_INITIALIZER_UNLOCKED
#endif
};
static portMUX_TYPE uart_selectlock = portMUX_INITIALIZER_UNLOCKED;
esp_err_t uart_set_word_length(uart_port_t uart_num, uart_word_length_t data_bit)
@ -528,9 +542,11 @@ esp_err_t uart_isr_register(uart_port_t uart_num, void (*fn)(void*), void * arg,
case UART_NUM_1:
ret=esp_intr_alloc(ETS_UART1_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
break;
#if UART_NUM > 2
case UART_NUM_2:
ret=esp_intr_alloc(ETS_UART2_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
break;
#endif
case UART_NUM_0:
default:
ret=esp_intr_alloc(ETS_UART0_INTR_SOURCE, intr_alloc_flags, fn, arg, handle);
@ -577,12 +593,14 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
rts_sig = U1RTS_OUT_IDX;
cts_sig = U1CTS_IN_IDX;
break;
#if UART_NUM > 2
case UART_NUM_2:
tx_sig = U2TXD_OUT_IDX;
rx_sig = U2RXD_IN_IDX;
rts_sig = U2RTS_OUT_IDX;
cts_sig = U2CTS_IN_IDX;
break;
#endif
case UART_NUM_MAX:
default:
tx_sig = U0TXD_OUT_IDX;
@ -656,8 +674,10 @@ esp_err_t uart_param_config(uart_port_t uart_num, const uart_config_t *uart_conf
periph_module_enable(PERIPH_UART0_MODULE);
} else if(uart_num == UART_NUM_1) {
periph_module_enable(PERIPH_UART1_MODULE);
#if UART_NUM > 2
} else if(uart_num == UART_NUM_2) {
periph_module_enable(PERIPH_UART2_MODULE);
#endif
}
r = uart_set_hw_flow_ctrl(uart_num, uart_config->flow_ctrl, uart_config->rx_flow_ctrl_thresh);
if (r != ESP_OK) return r;
@ -1460,8 +1480,10 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
periph_module_disable(PERIPH_UART0_MODULE);
} else if(uart_num == UART_NUM_1) {
periph_module_disable(PERIPH_UART1_MODULE);
#if UART_NUM > 2
} else if(uart_num == UART_NUM_2) {
periph_module_disable(PERIPH_UART2_MODULE);
#endif
}
}
return ESP_OK;

2
components/freemodbus/common/include/esp_modbus_common.h
View File

@ -24,7 +24,7 @@
// Default port defines
#define MB_DEVICE_ADDRESS (1) // Default slave device address in Modbus
#define MB_DEVICE_SPEED (115200) // Default Modbus speed for now hard defined
#define MB_UART_PORT (UART_NUM_2) // Default UART port number
#define MB_UART_PORT (UART_NUM_MAX - 1) // Default UART port number
#define MB_PAR_INFO_TOUT (10) // Timeout for get parameter info
#define MB_PARITY_NONE (UART_PARITY_DISABLE)

2
components/freemodbus/port/portserial.c
View File

@ -78,7 +78,7 @@ static TaskHandle_t xMbTaskHandle;
static const CHAR *TAG = "MB_SERIAL";
// The UART hardware port number
static UCHAR ucUartNumber = UART_NUM_2;
static UCHAR ucUartNumber = UART_NUM_MAX - 1;
static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag
static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag

2
components/freemodbus/port/portserial_m.c
View File

@ -73,7 +73,7 @@ static QueueHandle_t xMbUartQueue;
static TaskHandle_t xMbTaskHandle;
// The UART hardware port number
static UCHAR ucUartNumber = UART_NUM_2;
static UCHAR ucUartNumber = UART_NUM_MAX - 1;
static BOOL bRxStateEnabled = FALSE; // Receiver enabled flag
static BOOL bTxStateEnabled = FALSE; // Transmitter enabled flag

2
components/freemodbus/serial_master/modbus_controller/mbc_serial_master.c
View File

@ -83,7 +83,7 @@ static esp_err_t mbc_serial_master_setup(void* comm_info)
MB_MASTER_CHECK(((comm_info_ptr->mode == MB_MODE_RTU) || (comm_info_ptr->mode == MB_MODE_ASCII)),
ESP_ERR_INVALID_ARG, "mb incorrect mode = (0x%x).",
(uint32_t)comm_info_ptr->mode);
MB_MASTER_CHECK((comm_info_ptr->port <= UART_NUM_2), ESP_ERR_INVALID_ARG,
MB_MASTER_CHECK((comm_info_ptr->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG,
"mb wrong port to set = (0x%x).", (uint32_t)comm_info_ptr->port);
MB_MASTER_CHECK((comm_info_ptr->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG,
"mb wrong parity option = (0x%x).", (uint32_t)comm_info_ptr->parity);

2
components/freemodbus/serial_slave/modbus_controller/mbc_serial_slave.c
View File

@ -69,7 +69,7 @@ static esp_err_t mbc_serial_slave_setup(void* comm_info)
MB_SLAVE_CHECK((comm_settings->slave_addr <= MB_ADDRESS_MAX),
ESP_ERR_INVALID_ARG, "mb wrong slave address = (0x%x).",
(uint32_t)comm_settings->slave_addr);
MB_SLAVE_CHECK((comm_settings->port <= UART_NUM_2), ESP_ERR_INVALID_ARG,
MB_SLAVE_CHECK((comm_settings->port < UART_NUM_MAX), ESP_ERR_INVALID_ARG,
"mb wrong port to set = (0x%x).", (uint32_t)comm_settings->port);
MB_SLAVE_CHECK((comm_settings->parity <= UART_PARITY_EVEN), ESP_ERR_INVALID_ARG,
"mb wrong parity option = (0x%x).", (uint32_t)comm_settings->parity);

26
components/soc/esp32/include/soc/uart_caps.h Normal file
View File

@ -0,0 +1,26 @@
// Copyright 2017-2019 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#define SOC_UART_NUM 3
#ifdef __cplusplus
}
#endif

2
components/soc/include/soc/uart_periph.h
View File

@ -13,6 +13,8 @@
// limitations under the License.
#pragma once
#include "soc/uart_caps.h"
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/uart_channel.h"

185
components/vfs/vfs_uart.c
View File

@ -28,11 +28,27 @@
#include "esp32/rom/uart.h"
// TODO: make the number of UARTs chip dependent
#define UART_NUM 3
#define UART_NUM SOC_UART_NUM
// Token signifying that no character is available
#define NONE -1
#if CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_CR
#else
# define DEFAULT_TX_MODE ESP_LINE_ENDINGS_LF
#endif
#if CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDIN_LINE_ENDING_CR
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_CR
#else
# define DEFAULT_RX_MODE ESP_LINE_ENDINGS_LF
#endif
// UART write bytes function type
typedef void (*tx_func_t)(int, int);
// UART read bytes function type
@ -46,17 +62,54 @@ static int uart_rx_char(int fd);
static void uart_tx_char_via_driver(int fd, int c);
static int uart_rx_char_via_driver(int fd);
typedef struct {
// Pointers to UART peripherals
static uart_dev_t* s_uarts[UART_NUM] = {&UART0, &UART1, &UART2};
// per-UART locks, lazily initialized
static _lock_t s_uart_read_locks[UART_NUM];
static _lock_t s_uart_write_locks[UART_NUM];
uart_dev_t* uart;
// One-character buffer used for newline conversion code, per UART
static int s_peek_char[UART_NUM] = { NONE, NONE, NONE };
int peek_char;
// per-UART locks, lazily initialized
_lock_t read_lock;
_lock_t write_lock;
// Per-UART non-blocking flag. Note: default implementation does not honor this
// flag, all reads are non-blocking. This option becomes effective if UART
// driver is used.
static bool s_non_blocking[UART_NUM];
bool non_blocking;
// Newline conversion mode when transmitting
esp_line_endings_t tx_mode;
// Newline conversion mode when receiving
esp_line_endings_t rx_mode;
// Functions used to write bytes to UART. Default to "basic" functions.
tx_func_t tx_func;
// Functions used to read bytes from UART. Default to "basic" functions.
rx_func_t rx_func;
} vfs_uart_context_t;
#define VFS_CTX_DEFAULT_VAL(uart_dev) (vfs_uart_context_t) {\
.uart = (uart_dev),\
.peek_char = NONE,\
.tx_mode = DEFAULT_TX_MODE,\
.rx_mode = DEFAULT_RX_MODE,\
.tx_func = uart_tx_char,\
.rx_func = uart_rx_char,\
}
//If the context should be dynamically initialized, remove this structure
//and point s_ctx to allocated data.
static vfs_uart_context_t s_context[UART_NUM] = {
VFS_CTX_DEFAULT_VAL(&UART0),
VFS_CTX_DEFAULT_VAL(&UART1),
#if UART_NUM > 2
VFS_CTX_DEFAULT_VAL(&UART2),
#endif
};
static vfs_uart_context_t* s_ctx[UART_NUM] = {
&s_context[0],
&s_context[1],
#if UART_NUM > 2
&s_context[2],
#endif
};
/* Lock ensuring that uart_select is used from only one task at the time */
static _lock_t s_one_select_lock;
@ -69,39 +122,9 @@ static fd_set *_readfds_orig = NULL;
static fd_set *_writefds_orig = NULL;
static fd_set *_errorfds_orig = NULL;
// Newline conversion mode when transmitting
static esp_line_endings_t s_tx_mode =
#if CONFIG_NEWLIB_STDOUT_LINE_ENDING_CRLF
ESP_LINE_ENDINGS_CRLF;
#elif CONFIG_NEWLIB_STDOUT_LINE_ENDING_CR
ESP_LINE_ENDINGS_CR;
#else
ESP_LINE_ENDINGS_LF;
#endif
// Newline conversion mode when receiving
static esp_line_endings_t s_rx_mode[UART_NUM] = { [0 ... UART_NUM-1] =
#if CONFIG_NEWLIB_STDIN_LINE_ENDING_CRLF
ESP_LINE_ENDINGS_CRLF
#elif CONFIG_NEWLIB_STDIN_LINE_ENDING_CR
ESP_LINE_ENDINGS_CR
#else
ESP_LINE_ENDINGS_LF
#endif
};
static void uart_end_select();
// Functions used to write bytes to UART. Default to "basic" functions.
static tx_func_t s_uart_tx_func[UART_NUM] = {
&uart_tx_char, &uart_tx_char, &uart_tx_char
};
// Functions used to read bytes from UART. Default to "basic" functions.
static rx_func_t s_uart_rx_func[UART_NUM] = {
&uart_rx_char, &uart_rx_char, &uart_rx_char
};
static int uart_open(const char * path, int flags, int mode)
{
@ -120,14 +143,14 @@ static int uart_open(const char * path, int flags, int mode)
return fd;
}
s_non_blocking[fd] = ((flags & O_NONBLOCK) == O_NONBLOCK);
s_ctx[fd]->non_blocking = ((flags & O_NONBLOCK) == O_NONBLOCK);
return fd;
}
static void uart_tx_char(int fd, int c)
{
uart_dev_t* uart = s_uarts[fd];
uart_dev_t* uart = s_ctx[fd]->uart;
while (uart->status.txfifo_cnt >= 127) {
;
}
@ -142,7 +165,7 @@ static void uart_tx_char_via_driver(int fd, int c)
static int uart_rx_char(int fd)
{
uart_dev_t* uart = s_uarts[fd];
uart_dev_t* uart = s_ctx[fd]->uart;
if (uart->status.rxfifo_cnt == 0) {
return NONE;
}
@ -152,7 +175,7 @@ static int uart_rx_char(int fd)
static int uart_rx_char_via_driver(int fd)
{
uint8_t c;
int timeout = s_non_blocking[fd] ? 0 : portMAX_DELAY;
int timeout = s_ctx[fd]->non_blocking ? 0 : portMAX_DELAY;
int n = uart_read_bytes(fd, &c, 1, timeout);
if (n <= 0) {
return NONE;
@ -168,18 +191,18 @@ static ssize_t uart_write(int fd, const void * data, size_t size)
* a dedicated UART lock if two streams (stdout and stderr) point to the
* same UART.
*/
_lock_acquire_recursive(&s_uart_write_locks[fd]);
_lock_acquire_recursive(&s_ctx[fd]->write_lock);
for (size_t i = 0; i < size; i++) {
int c = data_c[i];
if (c == '\n' && s_tx_mode != ESP_LINE_ENDINGS_LF) {
s_uart_tx_func[fd](fd, '\r');
if (s_tx_mode == ESP_LINE_ENDINGS_CR) {
if (c == '\n' && s_ctx[fd]->tx_mode != ESP_LINE_ENDINGS_LF) {
s_ctx[fd]->tx_func(fd, '\r');
if (s_ctx[fd]->tx_mode == ESP_LINE_ENDINGS_CR) {
continue;
}
}
s_uart_tx_func[fd](fd, c);
s_ctx[fd]->tx_func(fd, c);
}
_lock_release_recursive(&s_uart_write_locks[fd]);
_lock_release_recursive(&s_ctx[fd]->write_lock);
return size;
}
@ -190,19 +213,19 @@ static ssize_t uart_write(int fd, const void * data, size_t size)
static int uart_read_char(int fd)
{
/* return character from peek buffer, if it is there */
if (s_peek_char[fd] != NONE) {
int c = s_peek_char[fd];
s_peek_char[fd] = NONE;
if (s_ctx[fd]->peek_char != NONE) {
int c = s_ctx[fd]->peek_char;
s_ctx[fd]->peek_char = NONE;
return c;
}
return s_uart_rx_func[fd](fd);
return s_ctx[fd]->rx_func(fd);
}
/* Push back a character; it will be returned by next call to uart_read_char */
static void uart_return_char(int fd, int c)
{
assert(s_peek_char[fd] == NONE);
s_peek_char[fd] = c;
assert(s_ctx[fd]->peek_char == NONE);
s_ctx[fd]->peek_char = c;
}
static ssize_t uart_read(int fd, void* data, size_t size)
@ -210,13 +233,13 @@ static ssize_t uart_read(int fd, void* data, size_t size)
assert(fd >=0 && fd < 3);
char *data_c = (char *) data;
size_t received = 0;
_lock_acquire_recursive(&s_uart_read_locks[fd]);
_lock_acquire_recursive(&s_ctx[fd]->read_lock);
while (received < size) {
int c = uart_read_char(fd);
if (c == '\r') {
if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CR) {
if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) {
c = '\n';
} else if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CRLF) {
} else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) {
/* look ahead */
int c2 = uart_read_char(fd);
if (c2 == NONE) {
@ -243,7 +266,7 @@ static ssize_t uart_read(int fd, void* data, size_t size)
break;
}
}
_lock_release_recursive(&s_uart_read_locks[fd]);
_lock_release_recursive(&s_ctx[fd]->read_lock);
if (received > 0) {
return received;
}
@ -269,11 +292,11 @@ static int uart_fcntl(int fd, int cmd, int arg)
assert(fd >=0 && fd < 3);
int result = 0;
if (cmd == F_GETFL) {
if (s_non_blocking[fd]) {
if (s_ctx[fd]->non_blocking) {
result |= O_NONBLOCK;
}
} else if (cmd == F_SETFL) {
s_non_blocking[fd] = (arg & O_NONBLOCK) != 0;
s_ctx[fd]->non_blocking = (arg & O_NONBLOCK) != 0;
} else {
// unsupported operation
result = -1;
@ -306,9 +329,9 @@ static int uart_access(const char *path, int amode)
static int uart_fsync(int fd)
{
assert(fd >= 0 && fd < 3);
_lock_acquire_recursive(&s_uart_write_locks[fd]);
_lock_acquire_recursive(&s_ctx[fd]->write_lock);
uart_tx_wait_idle((uint8_t) fd);
_lock_release_recursive(&s_uart_write_locks[fd]);
_lock_release_recursive(&s_ctx[fd]->write_lock);
return 0;
}
@ -477,11 +500,11 @@ static int uart_tcsetattr(int fd, int optional_actions, const struct termios *p)
}
if (p->c_iflag & IGNCR) {
s_rx_mode[fd] = ESP_LINE_ENDINGS_CRLF;
s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_CRLF;
} else if (p->c_iflag & ICRNL) {
s_rx_mode[fd] = ESP_LINE_ENDINGS_CR;
s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_CR;
} else {
s_rx_mode[fd] = ESP_LINE_ENDINGS_LF;
s_ctx[fd]->rx_mode = ESP_LINE_ENDINGS_LF;
}
// output line endings are not supported because there is no alternative in termios for converting LF to CR
@ -660,9 +683,9 @@ static int uart_tcgetattr(int fd, struct termios *p)
memset(p, 0, sizeof(struct termios));
if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CRLF) {
if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CRLF) {
p->c_iflag |= IGNCR;
} else if (s_rx_mode[fd] == ESP_LINE_ENDINGS_CR) {
} else if (s_ctx[fd]->rx_mode == ESP_LINE_ENDINGS_CR) {
p->c_iflag |= ICRNL;
}
@ -919,31 +942,33 @@ void esp_vfs_dev_uart_register()
void esp_vfs_dev_uart_set_rx_line_endings(esp_line_endings_t mode)
{
for (int i = 0; i < UART_NUM; ++i) {
s_rx_mode[i] = mode;
s_ctx[i]->rx_mode = mode;
}
}
void esp_vfs_dev_uart_set_tx_line_endings(esp_line_endings_t mode)
{
s_tx_mode = mode;
for (int i = 0; i < UART_NUM; ++i) {
s_ctx[i]->tx_mode = mode;
}
}
void esp_vfs_dev_uart_use_nonblocking(int uart_num)
{
_lock_acquire_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_uart_write_locks[uart_num]);
s_uart_tx_func[uart_num] = uart_tx_char;
s_uart_rx_func[uart_num] = uart_rx_char;
_lock_release_recursive(&s_uart_write_locks[uart_num]);
_lock_release_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_ctx[uart_num]->read_lock);
_lock_acquire_recursive(&s_ctx[uart_num]->write_lock);
s_ctx[uart_num]->tx_func = uart_tx_char;
s_ctx[uart_num]->rx_func = uart_rx_char;
_lock_release_recursive(&s_ctx[uart_num]->write_lock);
_lock_release_recursive(&s_ctx[uart_num]->read_lock);
}
void esp_vfs_dev_uart_use_driver(int uart_num)
{
_lock_acquire_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_uart_write_locks[uart_num]);
s_uart_tx_func[uart_num] = uart_tx_char_via_driver;
s_uart_rx_func[uart_num] = uart_rx_char_via_driver;
_lock_release_recursive(&s_uart_write_locks[uart_num]);
_lock_release_recursive(&s_uart_read_locks[uart_num]);
_lock_acquire_recursive(&s_ctx[uart_num]->read_lock);
_lock_acquire_recursive(&s_ctx[uart_num]->write_lock);
s_ctx[uart_num]->tx_func = uart_tx_char_via_driver;
s_ctx[uart_num]->rx_func = uart_rx_char_via_driver;
_lock_release_recursive(&s_ctx[uart_num]->write_lock);
_lock_release_recursive(&s_ctx[uart_num]->read_lock);
}