diff --git a/components/driver/test/include/test/test_common_spi.h b/components/driver/test/include/test/test_common_spi.h index fea4df7d01..469004975f 100644 --- a/components/driver/test/include/test/test_common_spi.h +++ b/components/driver/test/include/test/test_common_spi.h @@ -10,6 +10,7 @@ #include "test_utils.h" #include #include "param_test.h" +#include "soc/io_mux_reg.h" // All the tests using the header should use this definition as much as possible, // so that the working host can be changed easily in the future. @@ -30,7 +31,25 @@ #define SLAVE_PIN_NUM_CS VSPI_IOMUX_PIN_NUM_CS #define SLAVE_PIN_NUM_WP VSPI_IOMUX_PIN_NUM_WP #define SLAVE_PIN_NUM_HD VSPI_IOMUX_PIN_NUM_HD + +#define SLAVE_IOMUX_PIN_MISO VSPI_IOMUX_PIN_NUM_MISO +#define SLAVE_IOMUX_PIN_MOSI VSPI_IOMUX_PIN_NUM_MOSI +#define SLAVE_IOMUX_PIN_SCLK VSPI_IOMUX_PIN_NUM_CLK +#define SLAVE_IOMUX_PIN_CS VSPI_IOMUX_PIN_NUM_CS + +#define MASTER_IOMUX_PIN_MISO HSPI_IOMUX_PIN_NUM_MISO +#define MASTER_IOMUX_PIN_MOSI HSPI_IOMUX_PIN_NUM_MOSI +#define MASTER_IOMUX_PIN_SCLK HSPI_IOMUX_PIN_NUM_CLK +#define MASTER_IOMUX_PIN_CS HSPI_IOMUX_PIN_NUM_CS + +#define UNCONNECTED_PIN 27 +#define INPUT_ONLY_PIN 34 +#define GPIO_DELAY (12.5*2) +#define ESP_SPI_SLAVE_TV (12.5*3.5) +#define WIRE_DELAY 12.5 + #elif CONFIG_IDF_TARGET_ESP32S2BETA + #define TEST_SPI_HOST FSPI_HOST #define TEST_SLAVE_HOST HSPI_HOST @@ -47,16 +66,35 @@ #define SLAVE_PIN_NUM_CS HSPI_IOMUX_PIN_NUM_CS #define SLAVE_PIN_NUM_WP HSPI_IOMUX_PIN_NUM_WP #define SLAVE_PIN_NUM_HD HSPI_IOMUX_PIN_NUM_HD + +#define SLAVE_IOMUX_PIN_MISO -1 +#define SLAVE_IOMUX_PIN_MOSI -1 +#define SLAVE_IOMUX_PIN_SCLK -1 +#define SLAVE_IOMUX_PIN_CS -1 + +#define MASTER_IOMUX_PIN_MISO FSPI_IOMUX_PIN_NUM_MISO +#define MASTER_IOMUX_PIN_MOSI FSPI_IOMUX_PIN_NUM_MOSI +#define MASTER_IOMUX_PIN_SCLK FSPI_IOMUX_PIN_NUM_CLK +#define MASTER_IOMUX_PIN_CS FSPI_IOMUX_PIN_NUM_CS + +#define UNCONNECTED_PIN 41 +#define INPUT_ONLY_PIN 46 +#define GPIO_DELAY 0 +#define ESP_SPI_SLAVE_TV 0 +#define WIRE_DELAY 12.5 + #endif +#define GET_DMA_CHAN(HOST) (HOST) + +#define TEST_DMA_CHAN_MASTER GET_DMA_CHAN(TEST_SPI_HOST) +#define TEST_DMA_CHAN_SLAVE GET_DMA_CHAN(TEST_SLAVE_HOST) + #define FUNC_SPI 1 -#define FUNC_GPIO 2 +#define FUNC_GPIO PIN_FUNC_GPIO //Delay information -#define ESP_SPI_SLAVE_TV (12.5*3.5) -#define GPIO_DELAY (12.5*2) -#define WIRE_DELAY 12.5 #define TV_INT_CONNECT_GPIO (ESP_SPI_SLAVE_TV+GPIO_DELAY) #define TV_INT_CONNECT (ESP_SPI_SLAVE_TV) //when connecting to another board, the delay is usually increased by 12.5ns diff --git a/components/driver/test/test_common_spi.c b/components/driver/test/test_common_spi.c index be3beaed03..59bfc49e3e 100644 --- a/components/driver/test/test_common_spi.c +++ b/components/driver/test/test_common_spi.c @@ -87,7 +87,7 @@ void spitest_slave_task(void* arg) } while ( t.trans_len <= 2 ); memcpy(recvbuf, &t.trans_len, sizeof(uint32_t)); *(uint8_t**)(recvbuf+4) = (uint8_t*)txdata.start; - ESP_LOGI( SLAVE_TAG, "received: %d", t.trans_len ); + ESP_LOGD( SLAVE_TAG, "received: %d", t.trans_len ); xRingbufferSend( ringbuf, recvbuf, 8+(t.trans_len+7)/8, portMAX_DELAY ); } } @@ -161,19 +161,35 @@ void spitest_slave_print_data(slave_rxdata_t *t, bool print_rxdata) esp_err_t spitest_check_data(int len, spi_transaction_t *master_t, slave_rxdata_t *slave_t, bool check_master_data, bool check_slave_len, bool check_slave_data) { + esp_err_t ret = ESP_OK; + uint32_t rcv_len = slave_t->len; //currently the rcv_len can be in range of [t->length-1, t->length+3] - if (check_slave_len) { - uint32_t rcv_len = slave_t->len; - TEST_ASSERT(rcv_len >= len - 1 && rcv_len <= len + 4); + if (check_slave_len && + (rcv_len < len - 1 || rcv_len > len + 4)) { + ret = ESP_FAIL; } - if (check_master_data) { + if (check_master_data && + memcmp(slave_t->tx_start, master_t->rx_buffer, (len + 7) / 8) != 0 ) { + ret = ESP_FAIL; + } + + if (check_slave_data && + memcmp(master_t->tx_buffer, slave_t->data, (len + 7) / 8) != 0 ) { + ret = ESP_FAIL; + } + if (ret != ESP_OK) { + ESP_LOGI(SLAVE_TAG, "slave_recv_len: %d", rcv_len); + spitest_master_print_data(master_t, len); + spitest_slave_print_data(slave_t, true); + //already failed, try to use the TEST_ASSERT to output the reason... + if (check_slave_len) { + TEST_ASSERT(rcv_len >= len - 1 && rcv_len <= len + 4); + } TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t->tx_start, master_t->rx_buffer, (len + 7) / 8); - } - - if (check_slave_data) { TEST_ASSERT_EQUAL_HEX8_ARRAY(master_t->tx_buffer, slave_t->data, (len + 7) / 8); } + return ESP_OK; } diff --git a/components/driver/test/esp32/test_spi_master.c b/components/driver/test/test_spi_master.c similarity index 85% rename from components/driver/test/esp32/test_spi_master.c rename to components/driver/test/test_spi_master.c index 75ca7883b0..8dba1ee447 100644 --- a/components/driver/test/esp32/test_spi_master.c +++ b/components/driver/test/test_spi_master.c @@ -69,9 +69,9 @@ static void check_spi_pre_n_for(int clk, int pre, int n) TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") { spi_bus_config_t buscfg={ - .mosi_io_num=4, - .miso_io_num=26, - .sclk_io_num=25, + .mosi_io_num=PIN_NUM_MOSI, + .miso_io_num=PIN_NUM_MISO, + .sclk_io_num=PIN_NUM_CLK, .quadwp_io_num=-1, .quadhd_io_num=-1 }; @@ -93,11 +93,11 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]") TEST_ASSERT(ret==ESP_OK); } -static spi_device_handle_t setup_spi_bus(int clkspeed, bool dma) { +static spi_device_handle_t setup_spi_bus_loopback(int clkspeed, bool dma) { spi_bus_config_t buscfg={ - .mosi_io_num=26, - .miso_io_num=26, - .sclk_io_num=25, + .mosi_io_num=PIN_NUM_MOSI, + .miso_io_num=PIN_NUM_MOSI, + .sclk_io_num=PIN_NUM_CLK, .quadwp_io_num=-1, .quadhd_io_num=-1, .max_transfer_sz=4096*3 @@ -109,7 +109,7 @@ static spi_device_handle_t setup_spi_bus(int clkspeed, bool dma) { .clock_speed_hz=clkspeed, .duty_cycle_pos=128, .mode=0, - .spics_io_num=21, + .spics_io_num=PIN_NUM_CS, .queue_size=3, }; esp_err_t ret; @@ -120,7 +120,7 @@ static spi_device_handle_t setup_spi_bus(int clkspeed, bool dma) { ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle); TEST_ASSERT(ret==ESP_OK); //connect MOSI to two devices breaks the output, fix it. - spitest_gpio_output_sel(26, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); + spitest_gpio_output_sel(PIN_NUM_MOSI, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); printf("Bus/dev inited.\n"); return handle; } @@ -182,7 +182,7 @@ TEST_CASE("SPI Master test", "[spi]") { bool success = true; printf("Testing bus at 80KHz\n"); - spi_device_handle_t handle=setup_spi_bus(80000, true); + spi_device_handle_t handle=setup_spi_bus_loopback(80000, true); success &= spi_test(handle, 16); //small success &= spi_test(handle, 21); //small, unaligned success &= spi_test(handle, 36); //aligned @@ -195,7 +195,7 @@ TEST_CASE("SPI Master test", "[spi]") master_free_device_bus(handle); printf("Testing bus at 80KHz, non-DMA\n"); - handle=setup_spi_bus(80000, false); + handle=setup_spi_bus_loopback(80000, false); success &= spi_test(handle, 4); //aligned success &= spi_test(handle, 16); //small success &= spi_test(handle, 21); //small, unaligned @@ -207,14 +207,14 @@ TEST_CASE("SPI Master test", "[spi]") master_free_device_bus(handle); printf("Testing bus at 26MHz\n"); - handle=setup_spi_bus(20000000, true); + handle=setup_spi_bus_loopback(20000000, true); success &= spi_test(handle, 128); //DMA, aligned success &= spi_test(handle, 4096*3); //DMA, multiple descs master_free_device_bus(handle); printf("Testing bus at 900KHz\n"); - handle=setup_spi_bus(9000000, true); + handle=setup_spi_bus_loopback(9000000, true); success &= spi_test(handle, 128); //DMA, aligned success &= spi_test(handle, 4096*3); //DMA, multiple descs @@ -233,10 +233,10 @@ TEST_CASE("SPI Master test, interaction of multiple devs", "[spi]") { .clock_speed_hz=1000000, .duty_cycle_pos=128, .mode=0, - .spics_io_num=23, + .spics_io_num=PIN_NUM_CS, .queue_size=3, }; - spi_device_handle_t handle1=setup_spi_bus(80000, true); + spi_device_handle_t handle1=setup_spi_bus_loopback(80000, true); spi_device_handle_t handle2; spi_bus_add_device(TEST_SPI_HOST, &devcfg, &handle2); @@ -302,7 +302,7 @@ static esp_err_t test_slave_pins(int mosi, int miso, int sclk, int cs) spi_slave_interface_config_t slave_cfg = SPI_SLAVE_TEST_DEFAULT_CONFIG(); slave_cfg.spics_io_num = cs; - ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, 1); + ret = spi_slave_initialize(TEST_SLAVE_HOST, &cfg, &slave_cfg, TEST_DMA_CHAN_SLAVE); if (ret != ESP_OK) return ret; spi_slave_free(TEST_SLAVE_HOST); @@ -312,16 +312,16 @@ static esp_err_t test_slave_pins(int mosi, int miso, int sclk, int cs) TEST_CASE("spi placed on input-only pins", "[spi]") { TEST_ESP_OK(test_master_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS)); - TEST_ASSERT(test_master_pins(34, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS)!=ESP_OK); - TEST_ESP_OK(test_master_pins(PIN_NUM_MOSI, 34, PIN_NUM_CLK, PIN_NUM_CS)); - TEST_ASSERT(test_master_pins(PIN_NUM_MOSI, PIN_NUM_MISO, 34, PIN_NUM_CS)!=ESP_OK); - TEST_ASSERT(test_master_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, 34)!=ESP_OK); + TEST_ASSERT(test_master_pins(INPUT_ONLY_PIN, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS) != ESP_OK); + TEST_ESP_OK(test_master_pins(PIN_NUM_MOSI, INPUT_ONLY_PIN, PIN_NUM_CLK, PIN_NUM_CS)); + TEST_ASSERT(test_master_pins(PIN_NUM_MOSI, PIN_NUM_MISO, INPUT_ONLY_PIN, PIN_NUM_CS) != ESP_OK); + TEST_ASSERT(test_master_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN) != ESP_OK); TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS)); - TEST_ESP_OK(test_slave_pins(34, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS)); - TEST_ASSERT(test_slave_pins(PIN_NUM_MOSI, 34, PIN_NUM_CLK, PIN_NUM_CS)!=ESP_OK); - TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, 34, PIN_NUM_CS)); - TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, 34)); + TEST_ESP_OK(test_slave_pins(INPUT_ONLY_PIN, PIN_NUM_MISO, PIN_NUM_CLK, PIN_NUM_CS)); + TEST_ASSERT(test_slave_pins(PIN_NUM_MOSI, INPUT_ONLY_PIN, PIN_NUM_CLK, PIN_NUM_CS) != ESP_OK); + TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, INPUT_ONLY_PIN, PIN_NUM_CS)); + TEST_ESP_OK(test_slave_pins(PIN_NUM_MOSI, PIN_NUM_MISO, PIN_NUM_CLK, INPUT_ONLY_PIN)); } TEST_CASE("spi bus setting with different pin configs", "[spi]") @@ -332,7 +332,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 6 iomux output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_QUAD; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -341,7 +341,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 4 iomux output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_IOMUX_PINS | SPICOMMON_BUSFLAG_DUAL; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -351,7 +351,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 6 output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -361,7 +361,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test 4 output pins..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_DUAL; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -370,14 +370,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test master 5 output pins and MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 5 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_WPHD; - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -385,14 +385,14 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "test master 3 output pins and MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); ESP_LOGI(TAG, "test slave 3 output pins and MISO on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO; - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); TEST_ASSERT_EQUAL_HEX32( flags_expected, flags_o ); @@ -400,7 +400,7 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "check native flag for 6 output pins..."); flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); @@ -408,61 +408,61 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]") ESP_LOGI(TAG, "check native flag for 4 output pins..."); flags_expected = SPICOMMON_BUSFLAG_IOMUX_PINS; //swap MOSI and MISO - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check dual flag for master 5 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check dual flag for master 3 output pins and MISO/MOSI on input-only pin..."); flags_expected = SPICOMMON_BUSFLAG_DUAL; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = 34, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = INPUT_ONLY_PIN, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - cfg = (spi_bus_config_t){.mosi_io_num = 34, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = INPUT_ONLY_PIN, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check sclk flag..."); flags_expected = SPICOMMON_BUSFLAG_SCLK; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = -1, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check mosi flag..."); flags_expected = SPICOMMON_BUSFLAG_MOSI; - cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = -1, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check miso flag..."); flags_expected = SPICOMMON_BUSFLAG_MISO; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = -1, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); ESP_LOGI(TAG, "check quad flag..."); flags_expected = SPICOMMON_BUSFLAG_QUAD; - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[HSPI_HOST].spiwp_iomux_pin, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = -1, .quadwp_io_num = spi_periph_signal[TEST_SPI_HOST].spiwp_iomux_pin, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); - cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[HSPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[HSPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[HSPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[HSPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1, + cfg = (spi_bus_config_t){.mosi_io_num = spi_periph_signal[TEST_SPI_HOST].spid_iomux_pin, .miso_io_num = spi_periph_signal[TEST_SPI_HOST].spiq_iomux_pin, .sclk_io_num = spi_periph_signal[TEST_SPI_HOST].spiclk_iomux_pin, .quadhd_io_num = spi_periph_signal[TEST_SPI_HOST].spihd_iomux_pin, .quadwp_io_num = -1, .max_transfer_sz = 8, .flags = flags_expected}; TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_MASTER, &flags_o)); TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, 0, flags_expected|SPICOMMON_BUSFLAG_SLAVE, &flags_o)); @@ -475,14 +475,13 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" spi_device_interface_config_t device_config; spi_device_handle_t spi; spi_host_device_t host; - int dma = 1; memset(&bus_config, 0, sizeof(spi_bus_config_t)); memset(&device_config, 0, sizeof(spi_device_interface_config_t)); bus_config.miso_io_num = -1; - bus_config.mosi_io_num = 26; - bus_config.sclk_io_num = 25; + bus_config.mosi_io_num = PIN_NUM_MOSI; + bus_config.sclk_io_num = PIN_NUM_CLK; bus_config.quadwp_io_num = -1; bus_config.quadhd_io_num = -1; @@ -500,9 +499,9 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" }; //initialize for first host - host = 1; + host = TEST_SPI_HOST; - TEST_ASSERT(spi_bus_initialize(host, &bus_config, dma) == ESP_OK); + TEST_ASSERT(spi_bus_initialize(host, &bus_config, GET_DMA_CHAN(host)) == ESP_OK); TEST_ASSERT(spi_bus_add_device(host, &device_config, &spi) == ESP_OK); printf("before first xmit\n"); @@ -513,9 +512,9 @@ TEST_CASE("SPI Master no response when switch from host1 (HSPI) to host2 (VSPI)" TEST_ASSERT(spi_bus_free(host) == ESP_OK); //for second host and failed before - host = 2; + host = TEST_SLAVE_HOST; - TEST_ASSERT(spi_bus_initialize(host, &bus_config, dma) == ESP_OK); + TEST_ASSERT(spi_bus_initialize(host, &bus_config, GET_DMA_CHAN(host)) == ESP_OK); TEST_ASSERT(spi_bus_add_device(host, &device_config, &spi) == ESP_OK); printf("before second xmit\n"); @@ -729,6 +728,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) //initial master, mode 0, 1MHz spi_bus_config_t buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); + buscfg.quadhd_io_num = UNCONNECTED_PIN; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, 1)); spi_device_interface_config_t devcfg=SPI_DEVICE_TEST_DEFAULT_CONFIG(); devcfg.clock_speed_hz = 1*1000*1000; @@ -760,7 +760,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first) .base = { .flags = SPI_TRANS_VARIABLE_CMD | SPI_TRANS_VARIABLE_ADDR, .addr = 0x456789abcdef0123, - .cmd = 0xcdef, + .cmd = 0x9876, }, .command_bits = cmd_bits, .address_bits = addr_bits, @@ -942,7 +942,11 @@ TEST_CASE("SPI master variable dummy test", "[spi]") #define RECORD_TIME_PREPARE() uint32_t __t1, __t2 #define RECORD_TIME_START() do {__t1 = xthal_get_ccount();}while(0) #define RECORD_TIME_END(p_time) do{__t2 = xthal_get_ccount(); *p_time = (__t2-__t1);}while(0) -#define GET_US_BY_CCOUNT(t) ((t)/240.) +#ifdef CONFIG_IDF_TARGET_ESP32 +#define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#define GET_US_BY_CCOUNT(t) ((double)t/CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ) +#endif static void speed_setup(spi_device_handle_t* spi, bool use_dma) { @@ -952,7 +956,7 @@ static void speed_setup(spi_device_handle_t* spi, bool use_dma) devcfg.queue_size=8; //We want to be able to queue 7 transactions at a time //Initialize the SPI bus and the device to test - ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma?1:0)); + ret=spi_bus_initialize(TEST_SPI_HOST, &buscfg, (use_dma? GET_DMA_CHAN(TEST_SPI_HOST): 0)); TEST_ASSERT(ret==ESP_OK); ret=spi_bus_add_device(TEST_SPI_HOST, &devcfg, spi); TEST_ASSERT(ret==ESP_OK); diff --git a/components/driver/test/esp32/test_spi_param.c b/components/driver/test/test_spi_param.c similarity index 51% rename from components/driver/test/esp32/test_spi_param.c rename to components/driver/test/test_spi_param.c index e32156fbf4..095eabebdb 100644 --- a/components/driver/test/esp32/test_spi_param.c +++ b/components/driver/test/test_spi_param.c @@ -4,6 +4,7 @@ #include "esp_log.h" #include "soc/spi_periph.h" #include "test/test_common_spi.h" +#include "sdkconfig.h" /******************************************************************************** * Test By Internal Connections @@ -25,6 +26,7 @@ static const ptest_func_t local_test_func = { static void local_test_init(void** arg) { + esp_log_level_set("gpio", ESP_LOG_WARN); TEST_ASSERT(*arg==NULL); *arg = malloc(sizeof(spitest_context_t)); spitest_context_t* context = (spitest_context_t*)*arg; @@ -55,20 +57,20 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p assert(!pset->master_iomux || !pset->slave_iomux); if (pset->slave_iomux) { //only in this case, use VSPI iomux pins - buscfg.miso_io_num = VSPI_IOMUX_PIN_NUM_MISO; - buscfg.mosi_io_num = VSPI_IOMUX_PIN_NUM_MOSI; - buscfg.sclk_io_num = VSPI_IOMUX_PIN_NUM_CLK; - devcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS; - slvcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS; + buscfg.miso_io_num = SLAVE_IOMUX_PIN_MISO; + buscfg.mosi_io_num = SLAVE_IOMUX_PIN_MOSI; + buscfg.sclk_io_num = SLAVE_IOMUX_PIN_SCLK; + devcfg.spics_io_num = SLAVE_IOMUX_PIN_CS; + slvcfg.spics_io_num = SLAVE_IOMUX_PIN_CS; } else { - buscfg.miso_io_num = HSPI_IOMUX_PIN_NUM_MISO; - buscfg.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI; - buscfg.sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK; - devcfg.spics_io_num = HSPI_IOMUX_PIN_NUM_CS; - slvcfg.spics_io_num = HSPI_IOMUX_PIN_NUM_CS; + buscfg.miso_io_num = MASTER_IOMUX_PIN_MISO; + buscfg.mosi_io_num = MASTER_IOMUX_PIN_MOSI; + buscfg.sclk_io_num = MASTER_IOMUX_PIN_SCLK; + devcfg.spics_io_num = MASTER_IOMUX_PIN_CS; + slvcfg.spics_io_num = MASTER_IOMUX_PIN_CS; } //this does nothing, but avoid the driver from using iomux pins if required - buscfg.quadhd_io_num = (!pset->master_iomux && !pset->slave_iomux ? VSPI_IOMUX_PIN_NUM_MISO : -1); + buscfg.quadhd_io_num = (!pset->master_iomux && !pset->slave_iomux ? UNCONNECTED_PIN : -1); devcfg.mode = pset->mode; const int cs_pretrans_max = 15; if (pset->dup == HALF_DUPLEX_MISO) { @@ -100,26 +102,22 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p //initialize master and slave on the same pins break some of the output configs, fix them if (pset->master_iomux) { - spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_SPI, HSPID_OUT_IDX); - spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, VSPIQ_OUT_IDX); - spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_SPI, HSPICS0_OUT_IDX); - spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_SPI, HSPICLK_OUT_IDX); + spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_SPI, spi_periph_signal[TEST_SPI_HOST].spid_out); + spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out); + spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_SPI, spi_periph_signal[TEST_SPI_HOST].spics_out[0]); + spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_SPI, spi_periph_signal[TEST_SPI_HOST].spiclk_out); } else if (pset->slave_iomux) { - spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX); - spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_SPI, VSPIQ_OUT_IDX); - spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, HSPICS0_OUT_IDX); - spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, HSPICLK_OUT_IDX); + spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); + spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_SPI, spi_periph_signal[TEST_SLAVE_HOST].spiq_out); + spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]); + spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out); } else { - spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, HSPID_OUT_IDX); - spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, VSPIQ_OUT_IDX); - spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, HSPICS0_OUT_IDX); - spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, HSPICLK_OUT_IDX); + spitest_gpio_output_sel(buscfg.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out); + spitest_gpio_output_sel(buscfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out); + spitest_gpio_output_sel(devcfg.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[0]); + spitest_gpio_output_sel(buscfg.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out); } - //prepare slave tx data - for (int k = 0; k < pset->test_size; k++) - xQueueSend(context->slave_context.data_to_send, &context->slave_trans[k], portMAX_DELAY); - //clear master receive buffer memset(context->master_rxbuf, 0x66, sizeof(context->master_rxbuf)); @@ -139,35 +137,71 @@ static void local_test_loop(const void* arg1, void* arg2) if (freq==0) break; if (pset->freq_limit && freq > pset->freq_limit) break; - ESP_LOGI(MASTER_TAG, "======> %dk", freq / 1000); + ESP_LOGI(MASTER_TAG, "==> %dkHz", freq / 1000); + + bool check_master_data = (pset->dup!=HALF_DUPLEX_MOSI && + (pset->master_limit==0 || freq <= pset->master_limit)); + if (!check_master_data) ESP_LOGI(MASTER_TAG, "skip master data check"); + + bool check_slave_data = (pset->dup!=HALF_DUPLEX_MISO); + if (!check_slave_data) ESP_LOGI(SLAVE_TAG, "skip slave data check"); + local_test_start(&spi, freq, pset, context); for (int k = 0; k < pset->test_size; k++) { + WORD_ALIGNED_ATTR uint8_t recvbuf[320+8]; + slave_txdata_t *txdata = &context->slave_trans[k]; + spi_slave_transaction_t slave_trans = { + .tx_buffer = txdata->start, + .rx_buffer = recvbuf, + .length = txdata->len, + }; + esp_err_t err = spi_slave_queue_trans(TEST_SLAVE_HOST, &slave_trans, portMAX_DELAY); + TEST_ESP_OK(err); + //wait for both master and slave end - ESP_LOGI(MASTER_TAG, "=> test%d", k); - //send master tx data - vTaskDelay(9); - spi_transaction_t *t = &context->master_trans[k]; - TEST_ESP_OK(spi_device_transmit(spi, t)); int len = get_trans_len(pset->dup, t); - spitest_master_print_data(t, len); + ESP_LOGI(MASTER_TAG, " ==> #%d: len: %d", k, len); + //send master tx data - size_t rcv_len; - slave_rxdata_t *rcv_data = xRingbufferReceive(context->slave_context.data_received, &rcv_len, portMAX_DELAY); - spitest_slave_print_data(rcv_data, true); + err = spi_device_transmit(spi, t); + TEST_ESP_OK(err); - //check result - bool check_master_data = (pset->dup!=HALF_DUPLEX_MOSI && - (pset->master_limit==0 || freq <= pset->master_limit)); - bool check_slave_data = (pset->dup!=HALF_DUPLEX_MISO); - const bool check_len = true; - if (!check_master_data) ESP_LOGI(MASTER_TAG, "skip master data check"); - if (!check_slave_data) ESP_LOGI(SLAVE_TAG, "skip slave data check"); + spi_slave_transaction_t *ret_trans; + err = spi_slave_get_trans_result(TEST_SLAVE_HOST, &ret_trans, 5); + TEST_ESP_OK(err); + TEST_ASSERT_EQUAL(&slave_trans, ret_trans); - TEST_ESP_OK(spitest_check_data(len, t, rcv_data, check_master_data, check_len, check_slave_data)); - //clean - vRingbufferReturnItem(context->slave_context.data_received, rcv_data); + uint32_t rcv_len = slave_trans.trans_len; + bool failed = false; + + //check master data + if (check_master_data && memcmp(slave_trans.tx_buffer, t->rx_buffer, (len + 7) / 8) != 0 ) { + failed = true; + } + + //check slave data and length + //currently the rcv_len can be in range of [t->length-1, t->length+3] + if ( rcv_len < len - 1 || rcv_len > len + 4) { + failed = true; + } + if (check_slave_data && memcmp(t->tx_buffer, slave_trans.rx_buffer, (len + 7) / 8) != 0 ) { + failed = true; + } + + if (failed) { + ESP_LOGI(SLAVE_TAG, "slave_recv_len: %d", rcv_len); + spitest_master_print_data(t, len); + + ESP_LOG_BUFFER_HEX("slave tx", slave_trans.tx_buffer, len); + ESP_LOG_BUFFER_HEX("slave rx", slave_trans.rx_buffer, len); + + //already failed, try to use the TEST_ASSERT to output the reason... + TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_trans.tx_buffer, t->rx_buffer, (len + 7) / 8); + TEST_ASSERT_EQUAL_HEX8_ARRAY(t->tx_buffer, slave_trans.rx_buffer, (len + 7) / 8); + TEST_ASSERT(rcv_len >= len - 1 && rcv_len <= len + 4); + } } master_free_device_bus(spi); TEST_ASSERT(spi_slave_free(TEST_SLAVE_HOST) == ESP_OK); @@ -175,83 +209,88 @@ static void local_test_loop(const void* arg1, void* arg2) } /************ Timing Test ***********************************************/ +//TODO: esp32s2beta has better timing performance static spitest_param_set_t timing_pgroup[] = { - { .pset_name = "FULL_DUP, MASTER IOMUX", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .master_iomux = true, - .slave_iomux = false, - .slave_tv_ns = TV_INT_CONNECT_GPIO, +//signals are not fed to peripherals through iomux if the functions are not selected to iomux +#ifdef CONFIG_IDF_TARGET_ESP32 + { .pset_name = "FULL_DUP, MASTER IOMUX", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .master_iomux = true, + .slave_iomux = false, + .slave_tv_ns = TV_INT_CONNECT_GPIO, }, - { .pset_name = "FULL_DUP, SLAVE IOMUX", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "FULL_DUP, SLAVE IOMUX", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .master_iomux = false, + .slave_iomux = true, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "FULL_DUP, BOTH GPIO", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .master_limit = SPI_MASTER_FREQ_10M, - .dup = FULL_DUPLEX, - .master_iomux = false, - .slave_iomux = false, - .slave_tv_ns = TV_INT_CONNECT_GPIO, +#endif + { .pset_name = "FULL_DUP, BOTH GPIO", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .master_limit = SPI_MASTER_FREQ_10M, + .dup = FULL_DUPLEX, + .master_iomux = false, + .slave_iomux = false, + .slave_tv_ns = TV_INT_CONNECT_GPIO, }, - { .pset_name = "MISO_DUP, MASTER IOMUX", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .master_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .dup = HALF_DUPLEX_MISO, - .master_iomux = true, - .slave_iomux = false, - .slave_tv_ns = TV_INT_CONNECT_GPIO+12.5, - //for freq lower than 20M, the delay is 60(62.5)ns, however, the delay becomes 75ns over 26M +//signals are not fed to peripherals through iomux if the functions are not selected to iomux +#ifdef CONFIG_IDF_TARGET_ESP32 + { .pset_name = "MISO_DUP, MASTER IOMUX", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .master_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .dup = HALF_DUPLEX_MISO, + .master_iomux = true, + .slave_iomux = false, + .slave_tv_ns = TV_INT_CONNECT_GPIO, }, - { .pset_name = "MISO_DUP, SLAVE IOMUX", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - //.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .dup = HALF_DUPLEX_MISO, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT+12.5, - //for freq lower than 20M, the delay is 60(62.5)ns, however, the delay becomes 75ns over 26M - + { .pset_name = "MISO_DUP, SLAVE IOMUX", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + //.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .dup = HALF_DUPLEX_MISO, + .master_iomux = false, + .slave_iomux = true, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "MISO_DUP, BOTH GPIO", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - //.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .dup = HALF_DUPLEX_MISO, - .master_iomux = false, - .slave_iomux = false, - .slave_tv_ns = TV_INT_CONNECT_GPIO+12.5, - //for freq lower than 20M, the delay is 60(62.5)ns, however, the delay becomes 75ns over 26M - +#endif + { .pset_name = "MISO_DUP, BOTH GPIO", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + //.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .dup = HALF_DUPLEX_MISO, + .master_iomux = false, + .slave_iomux = false, + .slave_tv_ns = TV_INT_CONNECT_GPIO, }, - { .pset_name = "MOSI_DUP, MASTER IOMUX", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - //.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .dup = HALF_DUPLEX_MOSI, - .master_iomux = true, - .slave_iomux = false, - .slave_tv_ns = TV_INT_CONNECT_GPIO, +//signals are not fed to peripherals through iomux if the functions are not selected to iomux +#ifdef CONFIG_IDF_TARGET_ESP32 + { .pset_name = "MOSI_DUP, MASTER IOMUX", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + //.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .dup = HALF_DUPLEX_MOSI, + .master_iomux = true, + .slave_iomux = false, + .slave_tv_ns = TV_INT_CONNECT_GPIO, }, - { .pset_name = "MOSI_DUP, SLAVE IOMUX", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - //.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .dup = HALF_DUPLEX_MOSI, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "MOSI_DUP, SLAVE IOMUX", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + //.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .dup = HALF_DUPLEX_MOSI, + .master_iomux = false, + .slave_iomux = true, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "MOSI_DUP, BOTH GPIO", - .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, - //.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC, - .dup = HALF_DUPLEX_MOSI, - .master_iomux = false, - .slave_iomux = false, - .slave_tv_ns = TV_INT_CONNECT_GPIO, +#endif + { .pset_name = "MOSI_DUP, BOTH GPIO", + .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, + //.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC, + .dup = HALF_DUPLEX_MOSI, + .master_iomux = false, + .slave_iomux = false, + .slave_tv_ns = TV_INT_CONNECT_GPIO, }, }; TEST_SPI_LOCAL(TIMING, timing_pgroup) @@ -269,167 +308,196 @@ static int test_freq_mode_local[]={ 0, }; +//signals are not fed to peripherals through iomux if the functions are not selected to iomux +#ifdef CONFIG_IDF_TARGET_ESP32 +#define LOCAL_MODE_TEST_SLAVE_IOMUX true + +/* + * When DMA is enabled in mode 0 and 2, an special workaround is used. The MISO (slave's output) is + * half an SPI clock ahead, but then delay 3 apb clocks. + + * Compared to the normal timing, the MISO is not slower than when the frequency is below 13.3MHz, + * under which there's no need for the master to compensate the MISO signal. However compensation + * is required when the frequency is beyond 16MHz, at this time, an extra positive delay is added + * to the normal delay (3 apb clocks). + * + * It's is hard to tell the master driver that kind of delay logic. This magic delay value happens + * to compensate master timing beyond 16MHz. + * + * If the master or slave's timing is changed again, and the test no longer passes, above 16MHz, + * it's OK to use `master_limit` to disable master data check or skip the test above some + * frequencies above 10MHz (the design target value). + */ +#define SLAVE_EXTRA_DELAY_DMA 12.5 +#else +#define LOCAL_MODE_TEST_SLAVE_IOMUX false +#define SLAVE_EXTRA_DELAY_DMA 0 +#endif + + static spitest_param_set_t mode_pgroup[] = { - { .pset_name = "Mode 0", - .freq_list = test_freq_mode_local, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 0, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "Mode 0", + .freq_list = test_freq_mode_local, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 0, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "Mode 1", - .freq_list = test_freq_mode_local, - .freq_limit = SPI_MASTER_FREQ_26M, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 1, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "Mode 1", + .freq_list = test_freq_mode_local, + .freq_limit = SPI_MASTER_FREQ_26M, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 1, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "Mode 2", - .freq_list = test_freq_mode_local, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "Mode 2", + .freq_list = test_freq_mode_local, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "Mode 3", - .freq_list = test_freq_mode_local, - .freq_limit = SPI_MASTER_FREQ_26M, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 3, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "Mode 3", + .freq_list = test_freq_mode_local, + .freq_limit = SPI_MASTER_FREQ_26M, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 3, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "Mode 0, DMA", - .freq_list = test_freq_mode_local, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 0, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, //at 16M, the MISO delay (-0.5T+(3+2)apb) equals to non-DMA mode delay (3apb). - .length_aligned = true, + { .pset_name = "Mode 0, DMA", + .freq_list = test_freq_mode_local, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 0, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, + .length_aligned = true, }, - { .pset_name = "Mode 1, DMA", - .freq_list = test_freq_mode_local, - .freq_limit = SPI_MASTER_FREQ_26M, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 1, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, - .length_aligned = true, + { .pset_name = "Mode 1, DMA", + .freq_list = test_freq_mode_local, + .freq_limit = SPI_MASTER_FREQ_26M, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 1, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, + .length_aligned = true, }, - { .pset_name = "Mode 2, DMA", - .freq_list = test_freq_mode_local, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 2, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, //at 16M, the MISO delay (-0.5T+(3+2)apb) equals to non-DMA mode delay (3apb). - .length_aligned = true, + { .pset_name = "Mode 2, DMA", + .freq_list = test_freq_mode_local, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 2, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, + .length_aligned = true, }, - { .pset_name = "Mode 3, DMA", - .freq_list = test_freq_mode_local, - .freq_limit = SPI_MASTER_FREQ_26M, - .master_limit = SPI_MASTER_FREQ_13M, - .dup = FULL_DUPLEX, - .mode = 3, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, - .length_aligned = true, + { .pset_name = "Mode 3, DMA", + .freq_list = test_freq_mode_local, + .freq_limit = SPI_MASTER_FREQ_26M, + .master_limit = SPI_MASTER_FREQ_13M, + .dup = FULL_DUPLEX, + .mode = 3, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, + .length_aligned = true, }, - // MISO //////////////////////////////////// - { .pset_name = "MISO, Mode 0", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 0, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + /////////////////////////// MISO //////////////////////////////////// + { .pset_name = "MISO, Mode 0", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 0, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "MISO, Mode 1", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 1, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "MISO, Mode 1", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 1, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "MISO, Mode 2", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "MISO, Mode 2", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "MISO, Mode 3", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 3, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, + { .pset_name = "MISO, Mode 3", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 3, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, }, - { .pset_name = "MISO, Mode 0, DMA", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 0, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT+12.5, //at 16M, the MISO delay (-0.5T+(3+2)apb) equals to non-DMA mode delay (3apb). - .length_aligned = true, + { .pset_name = "MISO, Mode 0, DMA", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 0, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT+SLAVE_EXTRA_DELAY_DMA, + .length_aligned = true, }, - { .pset_name = "MISO, Mode 1, DMA", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 1, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, - .length_aligned = true, + { .pset_name = "MISO, Mode 1, DMA", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 1, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, + .length_aligned = true, }, - { .pset_name = "MISO, Mode 2, DMA", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 2, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT+12.5, //at 16M, the MISO delay (-0.5T+(3+2)apb) equals to non-DMA mode delay (3apb). - .length_aligned = true, + { .pset_name = "MISO, Mode 2, DMA", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 2, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT+SLAVE_EXTRA_DELAY_DMA, + .length_aligned = true, }, - { .pset_name = "MISO, Mode 3, DMA", - .freq_list = test_freq_mode_local, - .dup = HALF_DUPLEX_MISO, - .mode = 3, - .slave_dma_chan = 2, - .master_iomux = false, - .slave_iomux = true, - .slave_tv_ns = TV_INT_CONNECT, - .length_aligned = true, + { .pset_name = "MISO, Mode 3, DMA", + .freq_list = test_freq_mode_local, + .dup = HALF_DUPLEX_MISO, + .mode = 3, + .slave_dma_chan = 2, + .master_iomux = false, + .slave_iomux = LOCAL_MODE_TEST_SLAVE_IOMUX, + .slave_tv_ns = TV_INT_CONNECT, + .length_aligned = true, }, }; TEST_SPI_LOCAL(MODE, mode_pgroup) +#ifdef CONFIG_IDF_TARGET_ESP32 +//These tests are ESP32 only due to lack of runners /******************************************************************************** * Test By Master & Slave (2 boards) * @@ -465,9 +533,13 @@ static const ptest_func_t slave_test_func = { .def_param = spitest_def_param, }; -#define TEST_SPI_MASTER_SLAVE(name, param_group, extra_tag) \ +#ifdef CONFIG_IDF_TARGET_ESP32 +#define TEST_SPI_MASTER_SLAVE_ESP32(name, param_group, extra_tag) \ PARAM_GROUP_DECLARE(name, param_group) \ TEST_MASTER_SLAVE(name, param_group, "[spi_ms][test_env=Example_SPI_Multi_device][timeout=120]"#extra_tag, &master_test_func, &slave_test_func) +#else +#define TEST_SPI_MASTER_SLAVE_ESP32(name, param_group, extra_tag) +#endif /************ Master Code ***********************************************/ static void test_master_init(void** arg) @@ -491,13 +563,13 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_ { //master config spi_bus_config_t buspset=SPI_BUS_TEST_DEFAULT_CONFIG(); - buspset.miso_io_num = HSPI_IOMUX_PIN_NUM_MISO; - buspset.mosi_io_num = HSPI_IOMUX_PIN_NUM_MOSI; - buspset.sclk_io_num = HSPI_IOMUX_PIN_NUM_CLK; + buspset.miso_io_num = MASTER_IOMUX_PIN_MISO; + buspset.mosi_io_num = MASTER_IOMUX_PIN_MOSI; + buspset.sclk_io_num = MASTER_IOMUX_PIN_SCLK; //this does nothing, but avoid the driver from using native pins - if (!pset->master_iomux) buspset.quadhd_io_num = VSPI_IOMUX_PIN_NUM_MISO; + if (!pset->master_iomux) buspset.quadhd_io_num = UNCONNECTED_PIN; spi_device_interface_config_t devpset=SPI_DEVICE_TEST_DEFAULT_CONFIG(); - devpset.spics_io_num = HSPI_IOMUX_PIN_NUM_CS; + devpset.spics_io_num = MASTER_IOMUX_PIN_CS; devpset.mode = pset->mode; const int cs_pretrans_max = 15; if (pset->dup==HALF_DUPLEX_MISO) { @@ -623,13 +695,13 @@ static void timing_slave_start(int speed, const spitest_param_set_t* pset, spite { //slave config spi_bus_config_t slv_buscfg=SPI_BUS_TEST_DEFAULT_CONFIG(); - slv_buscfg.miso_io_num = VSPI_IOMUX_PIN_NUM_MISO; - slv_buscfg.mosi_io_num = VSPI_IOMUX_PIN_NUM_MOSI; - slv_buscfg.sclk_io_num = VSPI_IOMUX_PIN_NUM_CLK; + slv_buscfg.miso_io_num = SLAVE_IOMUX_PIN_MISO; + slv_buscfg.mosi_io_num = SLAVE_IOMUX_PIN_MOSI; + slv_buscfg.sclk_io_num = SLAVE_IOMUX_PIN_SCLK; //this does nothing, but avoid the driver from using native pins - if (!pset->slave_iomux) slv_buscfg.quadhd_io_num = HSPI_IOMUX_PIN_NUM_CLK; + if (!pset->slave_iomux) slv_buscfg.quadhd_io_num = UNCONNECTED_PIN; spi_slave_interface_config_t slvcfg=SPI_SLAVE_TEST_DEFAULT_CONFIG(); - slvcfg.spics_io_num = VSPI_IOMUX_PIN_NUM_CS; + slvcfg.spics_io_num = SLAVE_IOMUX_PIN_CS; slvcfg.mode = pset->mode; //Enable pull-ups on SPI lines so we don't detect rogue pulses when no master is connected. slave_pull_up(&slv_buscfg, slvcfg.spics_io_num); @@ -789,7 +861,7 @@ static spitest_param_set_t timing_conf[] = { .slave_tv_ns = TV_WITH_ESP_SLAVE_GPIO, }, }; -TEST_SPI_MASTER_SLAVE(TIMING, timing_conf, "") +TEST_SPI_MASTER_SLAVE_ESP32(TIMING, timing_conf, "") /************ Mode Test ***********************************************/ #define FREQ_LIMIT_MODE SPI_MASTER_FREQ_16M @@ -816,164 +888,166 @@ static int test_freq_20M_only[]={ spitest_param_set_t mode_conf[] = { //non-DMA tests - { .pset_name = "mode 0, no DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 0, + { .pset_name = "mode 0, no DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 0, }, - { .pset_name = "mode 1, no DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 1, + { .pset_name = "mode 1, no DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 1, }, - { .pset_name = "mode 2, no DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 2, + { .pset_name = "mode 2, no DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 2, }, - { .pset_name = "mode 3, no DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 3, + { .pset_name = "mode 3, no DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 3, }, //the master can only read to 16MHz, use half-duplex mode to read at 20. - { .pset_name = "mode 0, no DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 0, + { .pset_name = "mode 0, no DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 0, }, - { .pset_name = "mode 1, no DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 1, + { .pset_name = "mode 1, no DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 1, }, - { .pset_name = "mode 2, no DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 2, + { .pset_name = "mode 2, no DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 2, }, - { .pset_name = "mode 3, no DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 3, + { .pset_name = "mode 3, no DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 3, }, //DMA tests - { .pset_name = "mode 0, DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = DELAY_HCLK_UNTIL_7M, - .mode = 0, - .master_dma_chan = 1, - .slave_dma_chan = 1, - .length_aligned = true, + { .pset_name = "mode 0, DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = DELAY_HCLK_UNTIL_7M, + .mode = 0, + .master_dma_chan = 1, + .slave_dma_chan = 1, + .length_aligned = true, }, - { .pset_name = "mode 1, DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 1, - .master_dma_chan = 1, - .slave_dma_chan = 1, - .length_aligned = true, + { .pset_name = "mode 1, DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 1, + .master_dma_chan = 1, + .slave_dma_chan = 1, + .length_aligned = true, }, - { .pset_name = "mode 2, DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = DELAY_HCLK_UNTIL_7M, - .mode = 2, - .master_dma_chan = 1, - .slave_dma_chan = 1, - .length_aligned = true, + { .pset_name = "mode 2, DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = DELAY_HCLK_UNTIL_7M, + .mode = 2, + .master_dma_chan = 1, + .slave_dma_chan = 1, + .length_aligned = true, }, - { .pset_name = "mode 3, DMA", - .freq_list = test_freq_mode_ms, - .master_limit = FREQ_LIMIT_MODE, - .dup = FULL_DUPLEX, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 3, - .master_dma_chan = 1, - .slave_dma_chan = 1, - .length_aligned = true, + { .pset_name = "mode 3, DMA", + .freq_list = test_freq_mode_ms, + .master_limit = FREQ_LIMIT_MODE, + .dup = FULL_DUPLEX, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 3, + .master_dma_chan = 1, + .slave_dma_chan = 1, + .length_aligned = true, }, //the master can only read to 16MHz, use half-duplex mode to read at 20. - { .pset_name = "mode 0, DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 0, - .master_dma_chan = 1, - .slave_dma_chan = 1, + { .pset_name = "mode 0, DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 0, + .master_dma_chan = 1, + .slave_dma_chan = 1, }, - { .pset_name = "mode 1, DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 1, - .master_dma_chan = 1, - .slave_dma_chan = 1, + { .pset_name = "mode 1, DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 1, + .master_dma_chan = 1, + .slave_dma_chan = 1, }, - { .pset_name = "mode 2, DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 2, - .master_dma_chan = 1, - .slave_dma_chan = 1, + { .pset_name = "mode 2, DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 2, + .master_dma_chan = 1, + .slave_dma_chan = 1, }, - { .pset_name = "mode 3, DMA, 20M", - .freq_list = test_freq_20M_only, - .dup = HALF_DUPLEX_MISO, - .master_iomux= true, - .slave_iomux = true, - .slave_tv_ns = TV_WITH_ESP_SLAVE, - .mode = 3, - .master_dma_chan = 1, - .slave_dma_chan = 1, + { .pset_name = "mode 3, DMA, 20M", + .freq_list = test_freq_20M_only, + .dup = HALF_DUPLEX_MISO, + .master_iomux= true, + .slave_iomux = true, + .slave_tv_ns = TV_WITH_ESP_SLAVE, + .mode = 3, + .master_dma_chan = 1, + .slave_dma_chan = 1, }, }; -TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "[ignore]") +TEST_SPI_MASTER_SLAVE_ESP32(MODE, mode_conf, "") + +#endif \ No newline at end of file diff --git a/components/driver/test/esp32/test_spi_sio.c b/components/driver/test/test_spi_sio.c similarity index 92% rename from components/driver/test/esp32/test_spi_sio.c rename to components/driver/test/test_spi_sio.c index cb6964f6b8..c6fe8d65dc 100644 --- a/components/driver/test/esp32/test_spi_sio.c +++ b/components/driver/test/test_spi_sio.c @@ -7,7 +7,12 @@ #include #include #include +#include "sdkconfig.h" +#ifdef CONFIG_IDF_TARGET_ESP32 #include "esp32/rom/ets_sys.h" +#elif CONFIG_IDF_TARGET_ESP32S2BETA +#include "esp32s2beta/rom/ets_sys.h" +#endif #include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "freertos/semphr.h" @@ -22,7 +27,8 @@ #include "test_utils.h" #include "test/test_common_spi.h" #include "soc/gpio_periph.h" -#include "sdkconfig.h" + +#include "hal/spi_ll.h" /******************************************************************************** @@ -34,10 +40,9 @@ TEST_CASE("local test sio", "[spi]") WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320]; WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320]; - for (int i = 0; i < 16; i++) { - SPI1.data_buf[0] = 0xcccccccc; - SPI2.data_buf[0] = 0xcccccccc; - } + uint32_t pre_set[16] = {[0 ... 15] = 0xcccccccc,}; + spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SPI_HOST), (uint8_t*)pre_set, 16*32); + spi_ll_write_buffer(SPI_LL_GET_HW(TEST_SLAVE_HOST), (uint8_t*)pre_set, 16*32); /* This test use a strange connection to test the SIO mode: * master spid -> slave spid @@ -51,7 +56,7 @@ TEST_CASE("local test sio", "[spi]") int miso_io_num = bus_cfg.miso_io_num; int mosi_io_num = bus_cfg.mosi_io_num; - bus_cfg.mosi_io_num = bus_cfg.miso_io_num; + bus_cfg.mosi_io_num = miso_io_num; bus_cfg.miso_io_num = -1; TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, 0)); @@ -102,6 +107,8 @@ TEST_CASE("local test sio", "[spi]") master_free_device_bus(spi); } +#ifdef CONFIG_IDF_TARGET_ESP32 +//These tests are ESP32 only due to lack of runners /******************************************************************************** * Test SIO Master & Slave ********************************************************************************/ @@ -217,4 +224,5 @@ void test_sio_slave(void) test_sio_slave_round(false); } -TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave); +TEST_CASE_MULTIPLE_DEVICES_ESP32("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave); +#endif diff --git a/components/driver/test/esp32/test_spi_slave.c b/components/driver/test/test_spi_slave.c similarity index 99% rename from components/driver/test/esp32/test_spi_slave.c rename to components/driver/test/test_spi_slave.c index ba79393f51..9128d26341 100644 --- a/components/driver/test/esp32/test_spi_slave.c +++ b/components/driver/test/test_spi_slave.c @@ -31,7 +31,7 @@ static void master_init_nodma( spi_device_handle_t* spi) .miso_io_num=PIN_NUM_MISO, .mosi_io_num=PIN_NUM_MOSI, .sclk_io_num=PIN_NUM_CLK, - .quadwp_io_num=-1, + .quadwp_io_num=UNCONNECTED_PIN, .quadhd_io_num=-1 }; spi_device_interface_config_t devcfg={ diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h index 603408795b..72527687f2 100644 --- a/components/soc/esp32/include/soc/soc.h +++ b/components/soc/esp32/include/soc/soc.h @@ -221,7 +221,7 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 26*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define CPU_CLK_FREQ APB_CLK_FREQ +#define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP32_DEFAULT_CPU_FREQ_MHZ #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz #define REF_CLK_FREQ ( 1000000 ) #define UART_CLK_FREQ APB_CLK_FREQ