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spi_flash: enable cache access error test for all targets except ESP32-S2

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This commit is contained in:
Mahavir Jain 2021-10-12 09:55:45 +05:30
parent 61820f5b30
commit 11d9faf38c
2 changed files with 27 additions and 5 deletions
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31
components/spi_flash/test/test_cache_disabled.c
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@ -1,3 +1,9 @@
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@ -51,10 +57,18 @@ TEST_CASE("spi_flash_cache_enabled() works on both CPUs", "[spi_flash][esp_flash
vQueueDelete(result_queue);
}
static const uint32_t s_in_rodata[] = { 0x12345678, 0xfedcba98 };
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
// This needs to sufficiently large array, otherwise it may end up in
// DRAM (e.g. size <= 8 bytes && ARCH == RISCV)
static const uint32_t s_in_rodata[8] = { 0x12345678, 0xfedcba98 };
static void IRAM_ATTR cache_access_test_func(void* arg)
{
/* Assert that the array s_in_rodata is in DROM. If not, this test is
* invalid as disabling the cache wouldn't have any effect. */
TEST_ASSERT(esp_ptr_in_drom(s_in_rodata));
spi_flash_disable_interrupts_caches_and_other_cpu();
volatile uint32_t* src = (volatile uint32_t*) s_in_rodata;
uint32_t v1 = src[0];
@ -65,9 +79,17 @@ static void IRAM_ATTR cache_access_test_func(void* arg)
vTaskDelete(NULL);
}
#ifdef CONFIG_IDF_TARGET_ESP32C3
#define CACHE_ERROR_REASON "Cache error,RTC_SW_CPU_RST"
#elif CONFIG_IDF_TARGET_ESP32S3
#define CACHE_ERROR_REASON "Cache disabled,RTC_SW_CPU_RST"
#else
#define CACHE_ERROR_REASON "Cache disabled,SW_RESET"
#endif
// These tests works properly if they resets the chip with the
// "Cache disabled but cached memory region accessed" reason and the correct CPU is logged.
TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][ignore]")
TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]")
{
xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 0);
vTaskDelay(1000/portTICK_PERIOD_MS);
@ -75,10 +97,11 @@ TEST_CASE("invalid access to cache raises panic (PRO CPU)", "[spi_flash][ignore]
#ifndef CONFIG_FREERTOS_UNICORE
TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][ignore]")
TEST_CASE("invalid access to cache raises panic (APP CPU)", "[spi_flash][reset="CACHE_ERROR_REASON"]")
{
xTaskCreatePinnedToCore(&cache_access_test_func, "ia", 2048, NULL, 5, NULL, 1);
vTaskDelay(1000/portTICK_PERIOD_MS);
}
#endif
#endif // !CONFIG_FREERTOS_UNICORE
#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)

1
tools/ci/check_copyright_ignore.txt
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@ -2743,7 +2743,6 @@ components/spi_flash/spi_flash_chip_mxic_opi.c
components/spi_flash/spi_flash_chip_winbond.c
components/spi_flash/spi_flash_os_func_app.c
components/spi_flash/spi_flash_os_func_noos.c
components/spi_flash/test/test_cache_disabled.c
components/spi_flash/test/test_esp_flash.c
components/spi_flash/test/test_flash_encryption.c
components/spi_flash/test/test_large_flash_writes.c