From 69ab9d7a17724cb2358603dd10a2daa106950af3 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Fri, 14 Jun 2024 12:11:09 +0800 Subject: [PATCH 1/2] Revert "fix(rom): fixed esprv_int_set_threshold on C5" This reverts commit 171e0a21a14d6f9fb928787621ef4f49eafdb8b7. --- components/esp_rom/CMakeLists.txt | 2 +- .../esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in | 4 ---- components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h | 1 - .../esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld | 1 + components/esp_rom/patches/esp_rom_clic.c | 11 +---------- 5 files changed, 3 insertions(+), 16 deletions(-) diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt index ff207fad6f..859ebcd58a 100644 --- a/components/esp_rom/CMakeLists.txt +++ b/components/esp_rom/CMakeLists.txt @@ -69,7 +69,7 @@ if(CONFIG_HAL_WDT_USE_ROM_IMPL) list(APPEND sources "patches/esp_rom_wdt.c") endif() -if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH OR CONFIG_ESP_ROM_CLIC_INT_THRESH_PATCH) +if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH) list(APPEND sources "patches/esp_rom_clic.c") endif() diff --git a/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in index d162a71b74..11efd8b841 100644 --- a/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in +++ b/components/esp_rom/esp32c5/mp/esp32c5/Kconfig.soc_caps.in @@ -82,7 +82,3 @@ config ESP_ROM_HAS_VERSION config ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB bool default y - -config ESP_ROM_CLIC_INT_THRESH_PATCH - bool - default y diff --git a/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h index e1286bac1a..76b76bc17b 100644 --- a/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h +++ b/components/esp_rom/esp32c5/mp/esp32c5/esp_rom_caps.h @@ -28,4 +28,3 @@ #define ESP_ROM_RAM_APP_NEEDS_MMU_INIT (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init #define ESP_ROM_HAS_VERSION (1) // ROM has version/eco information #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. -#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF diff --git a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld index 8724419cc6..3f5b833a29 100644 --- a/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld +++ b/components/esp_rom/esp32c5/mp/esp32c5/ld/esp32c5.rom.ld @@ -276,6 +276,7 @@ gpio_pad_hold = 0x40000740; /* Functions */ esprv_intc_int_set_priority = 0x40000744; +esprv_intc_int_set_threshold = 0x40000748; esprv_intc_int_enable = 0x4000074c; esprv_intc_int_disable = 0x40000750; esprv_intc_int_set_type = 0x40000754; diff --git a/components/esp_rom/patches/esp_rom_clic.c b/components/esp_rom/patches/esp_rom_clic.c index 7160931c66..d4643e3ef5 100644 --- a/components/esp_rom/patches/esp_rom_clic.c +++ b/components/esp_rom/patches/esp_rom_clic.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,7 +7,6 @@ #include "esp_rom_caps.h" #include "soc/clic_reg.h" #include "riscv/interrupt.h" -#include "riscv/rv_utils.h" #if ESP_ROM_CLIC_INT_TYPE_PATCH @@ -21,11 +20,3 @@ void esprv_int_set_type(int rv_int_num, enum intr_type type) REG_SET_FIELD(CLIC_INT_CTRL_REG(rv_int_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_ATTR_TRIG, type); } #endif - -#if ESP_ROM_CLIC_INT_THRESH_PATCH -void esprv_int_set_threshold(int priority_threshold) -{ - /* ROM functions assume minimum MINTTHRESH is 0x1F, but it is actually 0xF */ - rv_utils_set_intlevel(priority_threshold); -} -#endif //ESP_ROM_CLIC_INT_THRESH_PATCH From d6eedc04bf020359396d6fa7752334bde1f5cc77 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Fri, 14 Jun 2024 12:11:19 +0800 Subject: [PATCH 2/2] Revert "fix(intr): fixed intr threshhold min level on C5" This reverts commit a6c2c4149d9424ba9476f6cb63cc6097bcab2edc. --- components/soc/esp32c5/mp/include/soc/clic_reg.h | 2 +- components/soc/esp32c61/include/soc/clic_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/soc/esp32c5/mp/include/soc/clic_reg.h b/components/soc/esp32c5/mp/include/soc/clic_reg.h index 35b8003fee..324cfd8c8a 100644 --- a/components/soc/esp32c5/mp/include/soc/clic_reg.h +++ b/components/soc/esp32c5/mp/include/soc/clic_reg.h @@ -10,7 +10,7 @@ extern "C" { #endif -#define NLBITS 4 +#define NLBITS 3 #define CLIC_EXT_INTR_NUM_OFFSET 16 #define DUALCORE_CLIC_CTRL_OFF 0x10000 diff --git a/components/soc/esp32c61/include/soc/clic_reg.h b/components/soc/esp32c61/include/soc/clic_reg.h index 219c175647..5ce606a178 100644 --- a/components/soc/esp32c61/include/soc/clic_reg.h +++ b/components/soc/esp32c61/include/soc/clic_reg.h @@ -10,7 +10,7 @@ extern "C" { #endif -#define NLBITS 4 +#define NLBITS 3 #define CLIC_EXT_INTR_NUM_OFFSET 16 #define DR_REG_CLIC_BASE (0x20800000)