esp_phy: Update ESP32S2 phy lib to support eco1 chip

This commit is contained in:
chenjianxing 2022-01-10 14:20:30 +08:00
parent fcce82ea53
commit 10c604475d
6 changed files with 92 additions and 59 deletions

View File

@ -15,10 +15,10 @@
#include "sdkconfig.h"
#include "bootloader_clock.h"
#include "bootloader_common.h"
#include "soc/efuse_reg.h"
uint8_t bootloader_common_get_chip_revision(void)
{
// should return the same value as esp_efuse_get_chip_ver()
/* No other revisions for ESP32-S2 */
return 0;
return REG_GET_FIELD(EFUSE_RD_MAC_SPI_SYS_3_REG, EFUSE_WAFER_VERSION);
}

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@ -34,7 +34,7 @@ uint8_t esp_efuse_get_chip_ver(void)
{
// should return the same value as bootloader_common_get_chip_revision()
uint32_t chip_ver = 0;
// TODO: ESP32S2 does not have this field
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}

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@ -44,64 +44,76 @@ static const char phy_init_magic_pre[] = PHY_INIT_MAGIC;
* @brief Structure containing default recommended PHY initialization parameters.
*/
static const esp_phy_init_data_t phy_init_data= { {
3,
0,
0x04,
0x05,
0x04,
0x05,
0x05,
0x04,
0x06,
0x06,
0x06,
0x05,
0x06,
0x80,
0x00,
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4E),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4E),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x44),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x44),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x44),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x42),
0x00,
0x00,
0x00,
0x00,
0x05,
0x09,
0x06,
0x05,
0x03,
0x06,
0x05,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0x00,
0xf4,
0xf8,
0xf8,
0xf0,
0xf0,
0xf0,
0xe0,
0xe0,
0xe0,
0x18,
0x18,
0x18,
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 78),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 72),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 66),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 60),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 56),
LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52),
0,
1,
1,
2,
2,
3,
4,
5,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0xff,
0,
0,
0,
@ -151,6 +163,15 @@ static const esp_phy_init_data_t phy_init_data= { {
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0xf1
} };
static const char phy_init_magic_post[] = PHY_INIT_MAGIC;

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@ -81,6 +81,13 @@ void phy_close_rf(void);
*/
uint8_t phy_dig_reg_backup(bool backup_en, uint32_t *mem_addr);
#if CONFIG_IDF_TARGET_ESP32S2
/**
* @brief Phy version select for ESP32S2
*/
void phy_eco_version_sel(uint8_t chip_ver);
#endif
#ifdef __cplusplus
}
#endif

@ -1 +1 @@
Subproject commit a59d0ed9d872255e04e44fd47595fb1a2495e4e1
Subproject commit 88afe19a1e1be3c56ebef0e2fb21bcdc2090ff2d

View File

@ -26,6 +26,7 @@
#include "esp_log.h"
#include "nvs.h"
#include "nvs_flash.h"
#include "esp_efuse.h"
#include "sdkconfig.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
@ -768,6 +769,10 @@ void esp_phy_load_cal_and_init(phy_rf_module_t module)
char * phy_version = get_phy_version_str();
ESP_LOGI(TAG, "phy_version %s", phy_version);
#if CONFIG_IDF_TARGET_ESP32S2
phy_eco_version_sel(esp_efuse_get_chip_ver());
#endif
esp_phy_calibration_data_t* cal_data =
(esp_phy_calibration_data_t*) calloc(sizeof(esp_phy_calibration_data_t), 1);
if (cal_data == NULL) {