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efuse: Adds major and minor versions and others

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This commit is contained in:
KonstantinKondrashov 2022-05-26 03:16:15 +08:00
parent fca7be2ddb
commit 0f8ff5aa15
77 changed files with 776 additions and 404 deletions
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3
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c
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@ -17,6 +17,7 @@
#include "soc/spi_reg.h"
#include "soc/soc_caps.h"
#include "soc/soc_pins.h"
#include "hal/efuse_hal.h"
#include "hal/gpio_hal.h"
#include "flash_qio_mode.h"
#include "bootloader_common.h"
@ -175,7 +176,7 @@ int bootloader_flash_get_wp_pin(void)
return ESP32_D2WD_WP_GPIO;
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4:
/* Same package IDs are used for ESP32-PICO-V3 and ESP32-PICO-D4, silicon version differentiates */
chip_ver = bootloader_common_get_chip_revision();
chip_ver = efuse_hal_get_major_chip_version();
return (chip_ver < 3) ? ESP32_D2WD_WP_GPIO : ESP32_PICO_V3_GPIO;
case EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302:
return ESP32_PICO_V3_GPIO;

7
components/bootloader_support/include/bootloader_common.h
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@ -189,13 +189,6 @@ int bootloader_common_select_otadata(const esp_ota_select_entry_t *two_otadata,
*/
esp_err_t bootloader_common_get_partition_description(const esp_partition_pos_t *partition, esp_app_desc_t *app_desc);
/**
* @brief Get chip revision
*
* @return Chip revision number
*/
uint8_t bootloader_common_get_chip_revision(void);
/**
* @brief Get chip package
*

2
components/bootloader_support/src/bootloader_clock_init.c
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@ -32,7 +32,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
* document). For rev. 0, switch to 240 instead if it has been enabled
* previously.
*/
if (efuse_hal_get_chip_revision() == 0 &&
if (efuse_hal_get_major_chip_version() == 0 &&
clk_ll_cpu_get_freq_mhz_from_pll() == CLK_LL_PLL_240M_FREQ_MHZ) {
cpu_freq_mhz = 240;
}

9
components/bootloader_support/src/bootloader_common_loader.c
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@ -17,6 +17,7 @@
#include "soc/gpio_periph.h"
#include "soc/rtc.h"
#include "soc/efuse_reg.h"
#include "hal/efuse_hal.h"
#include "hal/gpio_ll.h"
#include "esp_image_format.h"
#include "bootloader_sha.h"
@ -63,7 +64,13 @@ esp_err_t bootloader_common_check_chip_validity(const esp_image_header_t* img_hd
}
#ifndef CONFIG_IDF_ENV_FPGA
uint8_t revision = bootloader_common_get_chip_revision();
#if defined(CONFIG_IDF_TARGET_ESP32) || defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32C2) || defined(CONFIG_IDF_TARGET_ESP32H2)
uint8_t revision = efuse_hal_get_major_chip_version();
// min_chip_rev keeps the MAJOR wafer version for these chips
#else
uint8_t revision = efuse_hal_get_minor_chip_version();
// min_chip_rev keeps the MINOR wafer version for these chips
#endif
if (revision < img_hdr->min_chip_rev) {
/* To fix this error, please update mininum supported chip revision from configuration,
* located in TARGET (e.g. ESP32) specific options under "Component config" menu */

5
components/bootloader_support/src/bootloader_efuse.c
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@ -11,11 +11,6 @@
#include "hal/efuse_hal.h"
#include "esp_attr.h"
IRAM_ATTR uint8_t bootloader_common_get_chip_revision(void)
{
return efuse_hal_get_chip_revision();
}
IRAM_ATTR uint32_t bootloader_common_get_chip_ver_pkg(void)
{
return efuse_ll_get_chip_ver_pkg();

5
components/bootloader_support/src/bootloader_init.c
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@ -18,6 +18,7 @@
#include "esp_cpu.h"
#include "soc/rtc.h"
#include "hal/wdt_hal.h"
#include "hal/efuse_hal.h"
static const char *TAG = "boot";
@ -40,9 +41,7 @@ esp_err_t bootloader_read_bootloader_header(void)
esp_err_t bootloader_check_bootloader_validity(void)
{
/* read chip revision from efuse */
uint8_t revision = bootloader_common_get_chip_revision();
ESP_LOGI(TAG, "chip revision: %d", revision);
ESP_LOGI(TAG, "chip revision: V%03d", efuse_hal_chip_revision());
/* compare with the one set in bootloader image header */
if (bootloader_common_check_chip_validity(&bootloader_image_hdr, ESP_IMAGE_BOOTLOADER) != ESP_OK) {
return ESP_FAIL;

5
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
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@ -40,6 +40,7 @@
#include "esp_efuse.h"
#include "hal/mmu_hal.h"
#include "hal/cache_hal.h"
#include "hal/efuse_hal.h"
static const char *TAG = "boot.esp32c3";
@ -250,7 +251,7 @@ static inline void bootloader_hardware_init(void)
{
// This check is always included in the bootloader so it can
// print the minimum revision error message later in the boot
if (bootloader_common_get_chip_revision() < 3) {
if (efuse_hal_get_minor_chip_version() < 3) {
REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 1);
REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 12);
}
@ -263,7 +264,7 @@ static inline void bootloader_ana_reset_config(void)
For ECO2: fix brownout reset bug, support swt & brownout reset;
For ECO3: fix clock glitch reset bug, support all reset, include: swt & brownout & clock glitch reset.
*/
uint8_t chip_version = bootloader_common_get_chip_revision();
uint8_t chip_version = efuse_hal_get_minor_chip_version();
switch (chip_version) {
case 0:
case 1:

8
components/efuse/esp32/esp_efuse_fields.c
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@ -22,12 +22,6 @@ const static char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
return efuse_hal_get_chip_revision();
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{
@ -49,7 +43,7 @@ esp_err_t esp_efuse_disable_rom_download_mode(void)
{
#ifndef CONFIG_ESP32_REV_MIN_3
/* Check if we support this revision at all */
if(esp_efuse_get_chip_ver() < 3) {
if (efuse_hal_get_major_chip_version() < 3) {
return ESP_ERR_NOT_SUPPORTED;
}
#endif

13
components/efuse/esp32/esp_efuse_table.c
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table f552d73ac112985991efa6734a60c8d9
// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -160,6 +160,10 @@ static const esp_efuse_desc_t CHIP_VER_REV2[] = {
{EFUSE_BLK0, 180, 1}, // EFUSE_RD_CHIP_VER_REV2,
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK0, 184, 2}, // WAFER_VERSION_MINOR,
};
static const esp_efuse_desc_t XPD_SDIO_REG[] = {
{EFUSE_BLK0, 142, 1}, // EFUSE_RD_XPD_SDIO_REG,
};
@ -366,6 +370,11 @@ const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[] = {
&XPD_SDIO_REG[0], // EFUSE_RD_XPD_SDIO_REG
NULL

1
components/efuse/esp32/esp_efuse_table.csv
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@ -71,6 +71,7 @@ CHIP_CPU_FREQ_LOW, EFUSE_BLK0, 108, 1, EFUSE_RD_CHIP_CPU_FREQ_LOW
CHIP_CPU_FREQ_RATED, EFUSE_BLK0, 109, 1, EFUSE_RD_CHIP_CPU_FREQ_RATED
CHIP_VER_REV1, EFUSE_BLK0, 111, 1, EFUSE_RD_CHIP_VER_REV1
CHIP_VER_REV2, EFUSE_BLK0, 180, 1, EFUSE_RD_CHIP_VER_REV2
WAFER_VERSION_MINOR, EFUSE_BLK0, 184, 2, WAFER_VERSION_MINOR
XPD_SDIO_REG, EFUSE_BLK0, 142, 1, EFUSE_RD_XPD_SDIO_REG
SDIO_TIEH, EFUSE_BLK0, 143, 1, EFUSE_RD_SDIO_TIEH
SDIO_FORCE, EFUSE_BLK0, 144, 1, EFUSE_RD_SDIO_FORCE

Can't render this file because it contains an unexpected character in line 7 and column 87.

5
components/efuse/esp32/include/esp_efuse_table.h
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@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table f552d73ac112985991efa6734a60c8d9
// md5_digest_table 6256f9b7c6783e0b651bf52b5b162aa8
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -48,6 +48,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_LOW[];
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_CPU_FREQ_RATED[];
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV1[];
extern const esp_efuse_desc_t* ESP_EFUSE_CHIP_VER_REV2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_XPD_SDIO_REG[];
extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_TIEH[];
extern const esp_efuse_desc_t* ESP_EFUSE_SDIO_FORCE[];

8
components/efuse/esp32c2/esp_efuse_fields.c
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@ -21,14 +21,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

2
components/efuse/esp32c2/esp_efuse_rtc_calib.c
View File

@ -11,7 +11,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t result = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &result, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366
return result;
}

73
components/efuse/esp32c2/esp_efuse_table.c
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@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table af57e8a6a405ebf239cc552f713c91d0
// md5_digest_table ef050bc1e4bf0d8384aa3e4c0256d7d3
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -127,6 +127,18 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 54, 4}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t ENABLE_CUSTOM_MAC[] = {
{EFUSE_BLK0, 58, 1}, // True if MAC_CUSTOM is burned,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 59, 1}, // Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 60, 1}, // Disables check of blk version major,
};
static const esp_efuse_desc_t USER_DATA[] = {
{EFUSE_BLK1, 0, 88}, // User data block,
};
@ -144,24 +156,24 @@ static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK2, 0, 8}, // Factory MAC addr [5],
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK2, 48, 3}, // EFUSE_WAFER_VERSION,
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK2, 48, 4}, // WAFER_VERSION_MINOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK2, 52, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK2, 51, 3}, // EFUSE_PKG_VERSION,
{EFUSE_BLK2, 54, 3}, // EFUSE_PKG_VERSION,
};
static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 54, 3}, // EFUSE_BLOCK2_VERSION,
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK2, 57, 3}, // BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t RF_REF_I_BIAS_CONFIG[] = {
{EFUSE_BLK2, 57, 4}, // EFUSE_RF_REF_I_BIAS_CONFIG,
};
static const esp_efuse_desc_t LDO_VOL_BIAS_CONFIG_LOW[] = {
{EFUSE_BLK2, 61, 3}, // EFUSE_LDO_VOL_BIAS_CONFIG_LOW,
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK2, 60, 2}, // BLK_VERSION_MAJOR,
};
static const esp_efuse_desc_t LDO_VOL_BIAS_CONFIG_HIGH[] = {
@ -348,6 +360,21 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ENABLE_CUSTOM_MAC[] = {
&ENABLE_CUSTOM_MAC[0], // True if MAC_CUSTOM is burned
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
&USER_DATA[0], // User data block
NULL
@ -368,8 +395,13 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // EFUSE_WAFER_VERSION
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
@ -378,18 +410,13 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // EFUSE_BLOCK2_VERSION
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_RF_REF_I_BIAS_CONFIG[] = {
&RF_REF_I_BIAS_CONFIG[0], // EFUSE_RF_REF_I_BIAS_CONFIG
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_LDO_VOL_BIAS_CONFIG_LOW[] = {
&LDO_VOL_BIAS_CONFIG_LOW[0], // EFUSE_LDO_VOL_BIAS_CONFIG_LOW
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR
NULL
};

21
components/efuse/esp32c2/esp_efuse_table.csv
View File

@ -41,6 +41,9 @@
FLASH_TPUW, EFUSE_BLK0, 49, 4, Configure flash startup delay after SoC being powered up (the unit is ms/2). When the value is 15 delay will be 7.5 ms
SECURE_BOOT_EN, EFUSE_BLK0, 53, 1, Enable secure boot
SECURE_VERSION, EFUSE_BLK0, 54, 4, Secure version for anti-rollback
ENABLE_CUSTOM_MAC, EFUSE_BLK0, 58, 1, True if MAC_CUSTOM is burned
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 59, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 60, 1, Disables check of blk version major
# USER_DATA BLOCK# - System configuration
@ -51,6 +54,7 @@
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# EFUSE_RD_BLK2_DATA0_REG
MAC_FACTORY, EFUSE_BLK2, 40, 8, Factory MAC addr [0]
, EFUSE_BLK2, 32, 8, Factory MAC addr [1]
, EFUSE_BLK2, 24, 8, Factory MAC addr [2]
@ -58,19 +62,26 @@
, EFUSE_BLK2, 8, 8, Factory MAC addr [4]
, EFUSE_BLK2, 0, 8, Factory MAC addr [5]
WAFER_VERSION, EFUSE_BLK2, 48, 3, EFUSE_WAFER_VERSION
PKG_VERSION, EFUSE_BLK2, 51, 3, EFUSE_PKG_VERSION
BLOCK2_VERSION, EFUSE_BLK2, 54, 3, EFUSE_BLOCK2_VERSION
RF_REF_I_BIAS_CONFIG, EFUSE_BLK2, 57, 4, EFUSE_RF_REF_I_BIAS_CONFIG
LDO_VOL_BIAS_CONFIG_LOW, EFUSE_BLK2, 61, 3, EFUSE_LDO_VOL_BIAS_CONFIG_LOW
# EFUSE_RD_BLK2_DATA1_REG
# mac_id_high 16 bits
WAFER_VERSION_MINOR, EFUSE_BLK2, 48, 4, WAFER_VERSION_MINOR
WAFER_VERSION_MAJOR, EFUSE_BLK2, 52, 2, WAFER_VERSION_MAJOR
PKG_VERSION, EFUSE_BLK2, 54, 3, EFUSE_PKG_VERSION
BLK_VERSION_MINOR, EFUSE_BLK2, 57, 3, BLK_VERSION_MINOR
BLK_VERSION_MAJOR, EFUSE_BLK2, 60, 2, BLK_VERSION_MAJOR
# EFUSE_RD_BLK2_DATA2_REG
LDO_VOL_BIAS_CONFIG_HIGH, EFUSE_BLK2, 64, 27, EFUSE_LDO_VOL_BIAS_CONFIG_HIGH
PVT_LOW, EFUSE_BLK2, 91, 5, EFUSE_PVT_LOW
# EFUSE_RD_BLK2_DATA3_REG
PVT_HIGH, EFUSE_BLK2, 96, 10, EFUSE_PVT_HIGH
ADC_CALIBRATION_0, EFUSE_BLK2, 106, 22, EFUSE_ADC_CALIBRATION_0
# EFUSE_RD_BLK2_DATA4_REG
ADC_CALIBRATION_1, EFUSE_BLK2, 128, 32, EFUSE_ADC_CALIBRATION_1
# EFUSE_RD_BLK2_DATA5_REG
ADC_CALIBRATION_2, EFUSE_BLK2, 160, 32, EFUSE_ADC_CALIBRATION_2

Can't render this file because it contains an unexpected character in line 7 and column 53.

13
components/efuse/esp32c2/include/esp_efuse_table.h
View File

@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table af57e8a6a405ebf239cc552f713c91d0
// md5_digest_table ef050bc1e4bf0d8384aa3e4c0256d7d3
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -44,14 +44,17 @@ extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_CUSTOM_MAC[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_RF_REF_I_BIAS_CONFIG[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VOL_BIAS_CONFIG_LOW[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VOL_BIAS_CONFIG_HIGH[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_LOW[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_HIGH[];

8
components/efuse/esp32c3/esp_efuse_fields.c
View File

@ -21,14 +21,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

2
components/efuse/esp32c3/esp_efuse_rtc_calib.c
View File

@ -11,7 +11,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t result = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &result, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
return result;
}

55
components/efuse/esp32c3/esp_efuse_table.c
View File

@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
// md5_digest_table d006c80095638b5dbdc8649bf7e04dce
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -315,6 +315,14 @@ static const esp_efuse_desc_t ERR_RST_ENABLE[] = {
{EFUSE_BLK0, 159, 1}, // Use BLOCK0 to check error record registers,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 160, 1}, // Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 161, 1}, // Disables check of blk version major,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -368,24 +376,29 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version,
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits,
{EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 117, 3}, // Package version 0:ESP32C3,
};
static const esp_efuse_desc_t BLOCK1_VERSION[] = {
{EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version,
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 128, 3}, // Version of BLOCK2,
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2,
};
static const esp_efuse_desc_t TEMP_CALIB[] = {
@ -867,6 +880,16 @@ const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]
@ -932,8 +955,9 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // WAFER version
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits
&WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit
NULL
};
@ -942,8 +966,13 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
&BLOCK1_VERSION[0], // BLOCK1 efuse version
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
@ -952,8 +981,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // Version of BLOCK2
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2
NULL
};

22
components/efuse/esp32c3/esp_efuse_table.csv
View File

@ -98,10 +98,13 @@
ERR_RST_ENABLE, EFUSE_BLK0, 159, 1, Use BLOCK0 to check error record registers, 0 - without check.
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_SYS BLOCK#
#######################
# RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
@ -117,20 +120,33 @@
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
# RD_MAC_SPI_SYS_3
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
# RD_MAC_SPI_SYS_5
# WAFER_VERSION_MINOR most significant bit
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# RD_SYS_PART1_DATA0 - rd_sys_part1_data3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2
# RD_SYS_PART1_DATA4
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2
TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data
OCODE, EFUSE_BLK2, 140, 8, ADC OCode
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1
# RD_SYS_PART1_DATA5
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3
ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0

Can't render this file because it contains an unexpected character in line 7 and column 87.

11
components/efuse/esp32c3/include/esp_efuse_table.h
View File

@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 6614a99de35023cf9ba3849a2b80e9e7
// md5_digest_table d006c80095638b5dbdc8649bf7e04dce
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -91,6 +91,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_ERR_RST_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
@ -103,11 +105,12 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];

8
components/efuse/esp32h2/esp_efuse_fields.c
View File

@ -21,14 +21,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

9
components/efuse/esp32s2/esp_efuse_fields.c
View File

@ -20,15 +20,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
// should return the same value as bootloader_common_get_chip_revision()
uint32_t chip_ver = 0;
esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count);
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

2
components/efuse/esp32s2/esp_efuse_rtc_table.c
View File

@ -91,7 +91,7 @@ static const efuse_map_info_t adc_efuse_raw_map[] = {
int esp_efuse_rtc_table_read_calib_version(void)
{
uint32_t result = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 32);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &result, 3);
return result;
}

57
components/efuse/esp32s2/esp_efuse_table.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 614c862c2cfa8ccda3a79183ce767255
// md5_digest_table 3ac9188bf7eb0a27f3f636085a260743
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -331,6 +331,14 @@ static const esp_efuse_desc_t SECURE_VERSION[] = {
{EFUSE_BLK0, 139, 16}, // Secure version for anti-rollback,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 160, 1}, // Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 161, 1}, // Disables check of blk version major,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -384,16 +392,21 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 114, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 132, 3}, // WAFER_VERSION_MINOR least significant bits,
{EFUSE_BLK1, 116, 1}, // WAFER_VERSION_MINOR most significant bit,
};
static const esp_efuse_desc_t FLASH_VERSION[] = {
{EFUSE_BLK1, 117, 4}, // Flash_version,
};
static const esp_efuse_desc_t BLOCK1_VERSION[] = {
{EFUSE_BLK1, 121, 3}, // BLOCK1 efuse version,
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK1, 121, 2}, // BLK_VERSION_MAJOR,
};
static const esp_efuse_desc_t PSRAM_VERSION[] = {
@ -408,8 +421,8 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
static const esp_efuse_desc_t BLOCK2_VERSION[] = {
{EFUSE_BLK2, 132, 3}, // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK2, 132, 3}, // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2,
};
static const esp_efuse_desc_t USER_DATA[] = {
@ -847,6 +860,16 @@ const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]
@ -912,8 +935,14 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // WAFER version 0:A
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits
&WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit
NULL
};
@ -922,8 +951,8 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = {
&BLOCK1_VERSION[0], // BLOCK1 efuse version
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR
NULL
};
@ -942,8 +971,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = {
&BLOCK2_VERSION[0], // Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
NULL
};

21
components/efuse/esp32s2/esp_efuse_table.csv
View File

@ -102,10 +102,13 @@
SECURE_VERSION, EFUSE_BLK0, 139, 16, Secure version for anti-rollback
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_8M_SYS BLOCK#
#######################
# RD_MAC_SPI_8M_0 - RD_MAC_SPI_8M_2
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
@ -120,20 +123,30 @@
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
# RD_MAC_SPI_8M_3
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, WAFER_VERSION_MAJOR
WAFER_VERSION_MINOR, EFUSE_BLK1, 132, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 116, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR least significant bits is from RD_MAC_SPI_8M_4
FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version
BLOCK1_VERSION, EFUSE_BLK1, 121, 3, BLOCK1 efuse version
BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, BLK_VERSION_MAJOR
PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version
# RD_MAC_SPI_8M_4
PKG_VERSION, EFUSE_BLK1, 128, 4, Package version
# SYS_DATA_PART0, EFUSE_BLK1, 132, 60, System configuration (Reserve)
# WAFER_VERSION_MINOR least significant bits
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# RD_SYS_DATA0 - RD_SYS_DATA3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLOCK2_VERSION, EFUSE_BLK2, 132, 3, Version of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
# RD_SYS_DATA4
BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
################
USER_DATA, EFUSE_BLK3, 0, 256, User data

Can't render this file because it contains an unexpected character in line 7 and column 87.

13
components/efuse/esp32s2/include/esp_efuse_table.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 614c862c2cfa8ccda3a79183ce767255
// md5_digest_table 3ac9188bf7eb0a27f3f636085a260743
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -95,6 +95,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
@ -107,13 +109,14 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];

9
components/efuse/esp32s3/esp_efuse_fields.c
View File

@ -20,15 +20,6 @@ static __attribute__((unused)) const char *TAG = "efuse";
// Contains functions that provide access to efuse fields which are often used in IDF.
// Returns chip version from efuse
uint8_t esp_efuse_get_chip_ver(void)
{
// should return the same value as bootloader_common_get_chip_revision()
uint32_t chip_ver = 0;
// TODO: ESP32S2 does not have this field
return chip_ver;
}
// Returns chip package from efuse
uint32_t esp_efuse_get_pkg_ver(void)
{

2
components/efuse/esp32s3/esp_efuse_rtc_calib.c
View File

@ -14,7 +14,7 @@
int esp_efuse_rtc_calib_get_ver(void)
{
uint32_t blk_ver_major = 0;
ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_BLK_VER_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VER_MAJOR[0]->bit_count));
ESP_ERROR_CHECK(esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count)); // IDF-5366
uint32_t cali_version_v1 = (blk_ver_major == 1) ? 1 : 0;
if (!cali_version_v1) {

53
components/efuse/esp32s3/esp_efuse_table.c
View File

@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 62fa98bed350ebc4951c5f8191c487de
// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -355,6 +355,14 @@ static const esp_efuse_desc_t DIS_USB_OTG_DOWNLOAD_MODE[] = {
{EFUSE_BLK0, 159, 1}, // Set this bit to disable download through USB-OTG,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 160, 1}, // Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 161, 1}, // Disables check of blk version major,
};
static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 40, 8}, // Factory MAC addr [0],
{EFUSE_BLK1, 32, 8}, // Factory MAC addr [1],
@ -408,18 +416,23 @@ static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
};
static const esp_efuse_desc_t WAFER_VERSION[] = {
{EFUSE_BLK1, 114, 3}, // WAFER version 0:A,
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 114, 3}, // WAFER_VERSION_MINOR least significant bits,
{EFUSE_BLK1, 183, 1}, // WAFER_VERSION_MINOR most significant bit,
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 117, 3}, // Package version,
};
static const esp_efuse_desc_t BLK_VER_MINOR[] = {
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t ADC2_CAL_VOL_ATTEN3[] = {
{EFUSE_BLK1, 186, 6}, // ADC2 calibration voltage at atten3,
};
@ -428,8 +441,8 @@ static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
static const esp_efuse_desc_t BLK_VER_MAJOR[] = {
{EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR,
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK2, 128, 2}, // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware,
};
static const esp_efuse_desc_t TEMP_CALIB[] = {
@ -965,6 +978,16 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
&MAC_FACTORY[0], // Factory MAC addr [0]
&MAC_FACTORY[1], // Factory MAC addr [1]
@ -1030,8 +1053,9 @@ const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = {
&WAFER_VERSION[0], // WAFER version 0:A
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // WAFER_VERSION_MINOR least significant bits
&WAFER_VERSION_MINOR[1], // WAFER_VERSION_MINOR most significant bit
NULL
};
@ -1040,8 +1064,13 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MINOR[] = {
&BLK_VER_MINOR[0], // BLK_VERSION_MINOR
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // BLK_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
@ -1055,8 +1084,8 @@ const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MAJOR[] = {
&BLK_VER_MAJOR[0], // BLK_VERSION_MAJOR
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
NULL
};

22
components/efuse/esp32s3/esp_efuse_table.csv
View File

@ -107,6 +107,8 @@
DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 159, 1, Set this bit to disable download through USB-OTG
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_8M_SYS BLOCK#
@ -125,22 +127,36 @@
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
# RD_MAC_SPI_SYS_3
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version 0:A
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version
BLK_VER_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR, won't influence users
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
# RD_MAC_SPI_SYS_5
# WAFER_VERSION_MINOR most significant bit
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
ADC2_CAL_VOL_ATTEN3, EFUSE_BLK1, 186, 6, ADC2 calibration voltage at atten3
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# RD_SYS_PART1_DATA0
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
BLK_VER_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR, change of this bit means users need to update firmware
# RD_SYS_PART1_DATA4
BLK_VERSION_MAJOR, EFUSE_BLK2, 128, 2, BLK_VERSION_MAJOR of BLOCK2 change of this bit means users need to update firmware
TEMP_CALIB, EFUSE_BLK2, 132, 9, Temperature calibration data
OCODE, EFUSE_BLK2, 141, 8, ADC OCode
ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 149, 8, ADC1 init code at atten0
ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 157, 6, ADC1 init code at atten1
# RD_SYS_PART1_DATA5
ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 163, 6, ADC1 init code at atten2
ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 169, 6, ADC1 init code at atten3
ADC2_INIT_CODE_ATTEN0, EFUSE_BLK2, 175, 8, ADC2 init code at atten0

Can't render this file because it contains an unexpected character in line 8 and column 53.

11
components/efuse/esp32s3/include/esp_efuse_table.h
View File

@ -9,7 +9,7 @@ extern "C" {
#endif
// md5_digest_table 62fa98bed350ebc4951c5f8191c487de
// md5_digest_table 8c7a031bb0def28f2123ac5ee2a48d43
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -101,6 +101,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_OTG_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
@ -113,12 +115,13 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CAL_VOL_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VER_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[];

7
components/efuse/include/esp_efuse.h
View File

@ -278,13 +278,6 @@ esp_err_t esp_efuse_read_block(esp_efuse_block_t blk, void* dst_key, size_t offs
*/
esp_err_t esp_efuse_write_block(esp_efuse_block_t blk, const void* src_key, size_t offset_in_bits, size_t size_bits);
/**
* @brief Returns chip version from efuse
*
* @return chip version
*/
uint8_t esp_efuse_get_chip_ver(void);
/**
* @brief Returns chip package from efuse
*

6
components/efuse/test/test_efuse.c
View File

@ -865,9 +865,3 @@ TEST_CASE("Test chip_ver_pkg APIs return the same value", "[efuse]")
esp_efuse_utility_update_virt_blocks();
TEST_ASSERT_EQUAL_INT(esp_efuse_get_pkg_ver(), bootloader_common_get_chip_ver_pkg());
}
TEST_CASE("Test chip_revision APIs return the same value", "[efuse]")
{
esp_efuse_utility_update_virt_blocks();
TEST_ASSERT_EQUAL_INT(esp_efuse_get_chip_ver(), bootloader_common_get_chip_revision());
}

2
components/esp_hw_support/include/esp_chip_info.h
View File

@ -42,8 +42,8 @@ typedef enum {
typedef struct {
esp_chip_model_t model; //!< chip model, one of esp_chip_model_t
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint16_t revision; //!< chip revision number (in format MXX; where M - wafer major version, XX - wafer minor version)
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;
/**

4
components/esp_hw_support/port/esp32/chip_info.c
View File

@ -16,7 +16,7 @@ void esp_chip_info(esp_chip_info_t* out_info)
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
if (efuse_ll_get_disable_app_cpu() == 0) {
out_info->cores = 2;
@ -42,6 +42,6 @@ void esp_chip_info(esp_chip_info_t* out_info)
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
inline bool soc_has_cache_lock_bug(void)
{
return (efuse_hal_get_chip_revision() == 3);
return (efuse_hal_get_major_chip_version() == 3);
}
#endif

8
components/esp_hw_support/port/esp32/rtc_clk.c
View File

@ -45,7 +45,7 @@ static void rtc_clk_32k_enable_common(clk_ll_xtal32k_enable_mode_t mode)
SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
#ifdef CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
// version0 and version1 need provide additional current to external XTAL.
if(chip_ver == 0 || chip_ver == 1) {
/* TOUCH sensor can provide additional current to external XTAL.
@ -61,7 +61,7 @@ static void rtc_clk_32k_enable_common(clk_ll_xtal32k_enable_mode_t mode)
SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
}
#elif defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* TOUCH sensor can provide additional current to external XTAL.
In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
@ -95,13 +95,13 @@ void rtc_clk_32k_enable(bool enable)
CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
#ifdef CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* Power down TOUCH */
CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
}
#elif defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* Power down TOUCH */
CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);

2
components/esp_hw_support/port/esp32c2/chip_info.c
View File

@ -12,7 +12,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32C2;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}

5
components/esp_hw_support/port/esp32c2/rtc_init.c
View File

@ -14,6 +14,7 @@
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "hal/efuse_hal.h"
#include "regi2c_ctrl.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/regi2c_lp_bias.h"
@ -38,7 +39,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
rtc_calib_version = 0;
ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
@ -248,7 +249,7 @@ static void set_rtc_dig_dbias()
3. a reasonable rtc_dbias can be calculated by a certion formula.
*/
uint32_t rtc_dbias = 31, dig_dbias = 26;
uint8_t chip_version = esp_efuse_get_chip_ver();
uint8_t chip_version = efuse_hal_get_minor_chip_version();
if (chip_version >= 3) {
dig_dbias = get_dig_dbias_by_efuse(chip_version);
if (dig_dbias != 0) {

2
components/esp_hw_support/port/esp32c3/chip_info.c
View File

@ -12,7 +12,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32C3;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}

5
components/esp_hw_support/port/esp32c3/rtc_init.c
View File

@ -14,6 +14,7 @@
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "hal/efuse_hal.h"
#include "regi2c_ctrl.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/regi2c_lp_bias.h"
@ -52,7 +53,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
rtc_calib_version = 0;
ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
@ -316,7 +317,7 @@ static void set_rtc_dig_dbias()
3. a reasonable rtc_dbias can be calculated by a certion formula.
*/
uint32_t rtc_dbias = 28, dig_dbias = 28;
uint8_t chip_version = esp_efuse_get_chip_ver();
uint8_t chip_version = efuse_hal_get_minor_chip_version();
if (chip_version >= 3) {
dig_dbias = get_dig_dbias_by_efuse(chip_version);
if (dig_dbias != 0) {

4
components/esp_hw_support/port/esp32c3/rtc_sleep.c
View File

@ -21,7 +21,7 @@
#include "regi2c_ctrl.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/regi2c_lp_bias.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
/**
* Configure whether certain peripherals are powered down in deep sleep
@ -77,7 +77,7 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
if (sleep_flags & RTC_SLEEP_PD_DIG) {
unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
#if CONFIG_ESP32C3_REV_MIN < 3
if (esp_efuse_get_chip_ver() < 3) {
if (efuse_hal_get_minor_chip_version() < 3) {
atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */
}
#endif

2
components/esp_hw_support/port/esp32h2/chip_info.c
View File

@ -12,7 +12,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32H2;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;
}

2
components/esp_hw_support/port/esp32s2/chip_info.c
View File

@ -7,6 +7,7 @@
#include <string.h>
#include "esp_chip_info.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
@ -15,6 +16,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S2;
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN;

2
components/esp_hw_support/port/esp32s2/rtc_init.c
View File

@ -152,7 +152,7 @@ void rtc_init(rtc_config_t cfg)
#if !CONFIG_IDF_ENV_FPGA
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 32);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366
if (rtc_calib_version == 2) {
set_ocode_by_efuse(rtc_calib_version);
} else {

2
components/esp_hw_support/port/esp32s3/chip_info.c
View File

@ -6,11 +6,13 @@
#include <string.h>
#include "esp_chip_info.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S3;
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 2;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}

2
components/esp_hw_support/port/esp32s3/rtc_init.c
View File

@ -74,7 +74,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t blk_ver_major = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VER_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VER_MAJOR[0]->bit_count);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
blk_ver_major = 0;
ESP_HW_LOGW(TAG, "efuse read fail, set default blk_ver_major: %d\n", blk_ver_major);

3
components/esp_phy/src/phy_init.c
View File

@ -39,6 +39,7 @@
#elif CONFIG_IDF_TARGET_ESP32C2
#include "soc/syscon_reg.h"
#endif
#include "hal/efuse_hal.h"
#if CONFIG_IDF_TARGET_ESP32
extern wifi_mac_time_update_cb_t s_wifi_mac_time_update_cb;
@ -674,7 +675,7 @@ void esp_phy_load_cal_and_init(void)
ESP_LOGI(TAG, "phy_version %s", phy_version);
#if CONFIG_IDF_TARGET_ESP32S2
phy_eco_version_sel(esp_efuse_get_chip_ver());
phy_eco_version_sel(efuse_hal_get_major_chip_version());
#endif
esp_phy_calibration_data_t* cal_data =
(esp_phy_calibration_data_t*) calloc(sizeof(esp_phy_calibration_data_t), 1);

3
components/esp_psram/esp32/esp_psram_impl_quad.c
View File

@ -26,6 +26,7 @@
#include "soc/soc_caps.h"
#include "soc/spi_periph.h"
#include "driver/gpio.h"
#include "hal/efuse_hal.h"
#include "hal/gpio_hal.h"
#include "esp_private/spi_common_internal.h"
#include "esp_private/periph_ctrl.h"
@ -828,7 +829,7 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psra
}
psram_io.psram_clk_io = D2WD_PSRAM_CLK_IO;
psram_io.psram_cs_io = D2WD_PSRAM_CS_IO;
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && esp_efuse_get_chip_ver() >= 3) {
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && efuse_hal_get_major_chip_version() >= 3) {
ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
abort();
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {

5
components/hal/efuse_hal.c
View File

@ -17,3 +17,8 @@ void efuse_hal_get_mac(uint8_t *mac)
*((uint32_t*)&mac[0]) = efuse_ll_get_mac0();
*((uint16_t*)&mac[4]) = (uint16_t) efuse_ll_get_mac1();
}
uint32_t efuse_hal_chip_revision(void)
{
return efuse_hal_get_major_chip_version() * 100 + efuse_hal_get_minor_chip_version();
}

8
components/hal/esp32/efuse_hal.c
View File

@ -12,8 +12,7 @@
#include "hal/efuse_hal.h"
#include "soc/syscon_reg.h"
uint32_t efuse_hal_get_chip_revision(void)
uint32_t efuse_hal_get_major_chip_version(void)
{
uint8_t eco_bit0 = efuse_ll_get_chip_ver_rev1();
uint8_t eco_bit1 = efuse_ll_get_chip_ver_rev2();
@ -45,6 +44,11 @@ uint32_t efuse_hal_get_chip_revision(void)
return chip_ver;
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}
uint32_t efuse_hal_get_rated_freq_mhz(void)
{
//Check if ESP32 is rated for a CPU frequency of 160MHz only

5
components/hal/esp32/include/hal/efuse_hal.h
View File

@ -16,11 +16,6 @@
extern "C" {
#endif
/**
* @brief get chip version
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
* @brief get rated frequency in MHz
*/

13
components/hal/esp32/include/hal/efuse_ll.h
View File

@ -98,16 +98,29 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
return (pkg_version_4bit << 3) | pkg_version;
}
// use efuse_hal_get_major_chip_version() to get full major chip version
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev1(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1);
}
// use efuse_hal_get_major_chip_version() to get full major chip version
__attribute__((always_inline)) static inline bool efuse_ll_get_chip_ver_rev2(void)
{
return REG_GET_BIT(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2);
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_WAFER_VERSION_MINOR);
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return false;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_coding_scheme(void)
{
return REG_GET_FIELD(EFUSE_BLK0_RDATA6_REG, EFUSE_CODING_SCHEME);

9
components/hal/esp32c2/efuse_hal.c
View File

@ -13,9 +13,14 @@
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
uint32_t efuse_hal_get_chip_revision(void)
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_revision();
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}
/******************* eFuse control functions *************************/

6
components/hal/esp32c2/include/hal/efuse_hal.h
View File

@ -16,12 +16,6 @@
extern "C" {
#endif
/**
* @brief get chip version
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
* @brief set eFuse timings
*

31
components/hal/esp32c2/include/hal/efuse_ll.h
View File

@ -45,9 +45,36 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
return EFUSE.rd_repeat_data0.secure_boot_en;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void)
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_blk2_data1.wafer_version;
return EFUSE.rd_blk2_data1.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return EFUSE.rd_blk2_data1.wafer_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_repeat_data0.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_blk2_data1.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_blk2_data1.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_repeat_data0.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)

9
components/hal/esp32c3/efuse_hal.c
View File

@ -14,9 +14,14 @@
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
uint32_t efuse_hal_get_chip_revision(void)
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_revision();
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}
/******************* eFuse control functions *************************/

6
components/hal/esp32c3/include/hal/efuse_hal.h
View File

@ -16,12 +16,6 @@
extern "C" {
#endif
/**
* @brief get chip version
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
* @brief set eFuse timings
*

31
components/hal/esp32c3/include/hal/efuse_ll.h
View File

@ -50,9 +50,36 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_err_rst_enable(vo
return EFUSE.rd_repeat_data3.err_rst_enable;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void)
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_sys_3.wafer_version;
return EFUSE.rd_mac_spi_sys_5.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_sys_part1_data4.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_mac_spi_sys_3.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)

9
components/hal/esp32h2/efuse_hal.c
View File

@ -13,9 +13,14 @@
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
uint32_t efuse_hal_get_chip_revision(void)
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_revision();
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}
/******************* eFuse control functions *************************/

6
components/hal/esp32h2/include/hal/efuse_hal.h
View File

@ -16,12 +16,6 @@
extern "C" {
#endif
/**
* @brief get chip version
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
* @brief set eFuse timings
*

29
components/hal/esp32h2/include/hal/efuse_ll.h
View File

@ -45,11 +45,38 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
return EFUSE.rd_repeat_data2.secure_boot_en;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void)
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_sys_3.wafer_version;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return 0;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return 0;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
return EFUSE.rd_mac_spi_sys_3.pkg_version;

9
components/hal/esp32s2/efuse_hal.c
View File

@ -14,9 +14,14 @@
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
uint32_t efuse_hal_get_chip_revision(void)
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_revision();
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}
/******************* eFuse control functions *************************/

6
components/hal/esp32s2/include/hal/efuse_hal.h
View File

@ -15,12 +15,6 @@
extern "C" {
#endif
/**
* @brief get chip version
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
* @brief set eFuse timings
*

31
components/hal/esp32s2/include/hal/efuse_ll.h
View File

@ -45,9 +45,36 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
return EFUSE.rd_repeat_data2.secure_boot_en;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void)
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return EFUSE.rd_mac_spi_8m_3.wafer_version;
return EFUSE.rd_mac_spi_8m_3.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_8m_3.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_8m_4.wafer_version_minor_low;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_mac_spi_8m_3.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_sys_data4.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)

9
components/hal/esp32s3/efuse_hal.c
View File

@ -14,9 +14,14 @@
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
uint32_t efuse_hal_get_chip_revision(void)
uint32_t efuse_hal_get_major_chip_version(void)
{
return efuse_ll_get_chip_revision();
return efuse_ll_get_chip_wafer_version_major();
}
uint32_t efuse_hal_get_minor_chip_version(void)
{
return efuse_ll_get_chip_wafer_version_minor();
}
/******************* eFuse control functions *************************/

6
components/hal/esp32s3/include/hal/efuse_hal.h
View File

@ -16,12 +16,6 @@
extern "C" {
#endif
/**
* @brief get chip version
*/
uint32_t efuse_hal_get_chip_revision(void);
/**
* @brief set eFuse timings
*

31
components/hal/esp32s3/include/hal/efuse_ll.h
View File

@ -50,9 +50,36 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
return EFUSE.rd_repeat_data2.reg_secure_boot_en;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_revision(void)
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
return 0;
return EFUSE.rd_mac_spi_sys_5.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
return (EFUSE.rd_mac_spi_sys_5.wafer_version_minor_high << 3) + EFUSE.rd_mac_spi_sys_3.wafer_version_minor_low;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
return EFUSE.rd_sys_part1_data4.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
return EFUSE.rd_mac_spi_sys_3.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
return EFUSE.rd_repeat_data4.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)

17
components/hal/include/hal/efuse_hal.h
View File

@ -19,6 +19,23 @@ extern "C" {
*/
void efuse_hal_get_mac(uint8_t *mac);
/**
* @brief Returns chip version
*
* @return Chip version in format: Major * 100 + Minor
*/
uint32_t efuse_hal_chip_revision(void);
/**
* @brief Returns major chip version
*/
uint32_t efuse_hal_get_major_chip_version(void);
/**
* @brief Returns minor chip version
*/
uint32_t efuse_hal_get_minor_chip_version(void);
#ifdef __cplusplus
}
#endif

15
components/soc/esp32/include/soc/efuse_reg.h
View File

@ -200,15 +200,12 @@
#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V)<<(EFUSE_RD_FLASH_CRYPT_CONFIG_S))
#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xF
#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28
/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; */
/*descritpion: This field stores the difference between the digital regulator voltage at level6 and 1.2 V. (RO)
BIT[27] is the sign bit, 0: + , 1: -
BIT[26:24] is the difference value, unit: 0.017V
volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + BIT[26:24] * 0.017 */
#define EFUSE_RD_DIG_VOL_L6 0x0F
#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V)<<(EFUSE_RD_DIG_VOL_L6_S))
#define EFUSE_RD_DIG_VOL_L6_V 0x0F
#define EFUSE_RD_DIG_VOL_L6_S 24
/* EFUSE_RD_WAFER_VERSION_MINOR: RO; bitpos:[25:24]; */
/*descritpion: Wafer version minor*/
#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003
#define EFUSE_RD_WAFER_VERSION_MINOR_M ((EFUSE_RD_WAFER_VERSION_MINOR_V)<<(EFUSE_RD_WAFER_VERSION_MINOR_S))
#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x03
#define EFUSE_RD_WAFER_VERSION_MINOR_S 24
/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */
/*description: This field stores the voltage level for CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz.
0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)*/

50
components/soc/esp32c2/include/soc/efuse_struct.h
View File

@ -236,10 +236,26 @@ typedef union {
* The bit be set to enable secure boot.
*/
uint32_t secure_boot_en:1;
/** rpt4_reserved : RO; bitpos: [31:22]; default: 0;
/** secure_version : RO; bitpos: [25:22]; default: 0;
* Secure version for anti-rollback.
*/
uint32_t secure_version:4;
/** enable_custom_mac : RO; bitpos: [26]; default: 0;
* True if custom_mac is burned.
*/
uint32_t enable_custom_mac:1;
/** disable_wafer_version_major : RO; bitpos: [27]; default: 0;
* Disables check of wafer version major.
*/
uint32_t disable_wafer_version_major:1;
/** disable_blk_version_major : RO; bitpos: [28]; default: 0;
* Disables check of blk version major.
*/
uint32_t disable_blk_version_major:1;
/** rpt4_reserved : RO; bitpos: [31:29]; default: 0;
* Reserved (used for four backups method).
*/
uint32_t rpt4_reserved:10;
uint32_t rpt4_reserved:3;
};
uint32_t val;
} efuse_rd_repeat_data0_reg_t;
@ -306,26 +322,30 @@ typedef union {
* Store the bit [31:47] of MAC.
*/
uint32_t mac_id_high:16;
/** wafer_version : RO; bitpos: [18:16]; default: 0;
* Store wafer version.
/** wafer_version_minor : RO; bitpos: [19:16]; default: 0;
* Store wafer version minor.
*/
uint32_t wafer_version:3;
/** pkg_version : RO; bitpos: [21:19]; default: 0;
uint32_t wafer_version_minor:4;
/** wafer_version_major : RO; bitpos: [21:20]; default: 0;
* Store wafer version major.
*/
uint32_t wafer_version_major:2;
/** pkg_version : RO; bitpos: [24:22]; default: 0;
* Store package version.
*/
uint32_t pkg_version:3;
/** blk2_efuse_version : RO; bitpos: [24:22]; default: 0;
* Store efuse version.
/** blk_version_minor : RO; bitpos: [27:25]; default: 0;
* Store blk 2 efuse version minor.
*/
uint32_t blk2_efuse_version:3;
/** rf_ref_i_bias_config : RO; bitpos: [28:25]; default: 0;
* Store rf configuration parameters.
uint32_t blk_version_minor:3;
/** blk_version_major : RO; bitpos: [29:28]; default: 0;
* Store blk 2 efuse version major.
*/
uint32_t rf_ref_i_bias_config:4;
/** ldo_vol_bias_config_low : RO; bitpos: [31:29]; default: 0;
* Store the bit [0:2] of ido configuration parameters.
uint32_t blk_version_major:2;
/** reserve1 : RO; bitpos: [31:30]; default: 0;
* Store reserve1.
*/
uint32_t ldo_vol_bias_config_low:3;
uint32_t reserve1:2;
};
uint32_t val;
} efuse_rd_blk2_data1_reg_t;

27
components/soc/esp32c3/include/soc/efuse_struct.h
View File

@ -164,7 +164,9 @@ typedef volatile struct efuse_dev_s {
} rd_repeat_data3;
union {
struct {
uint32_t rpt4_reserved4:24; /*Reserved.*/
uint32_t disable_wafer_version_major: 1;
uint32_t disable_blk_version_major: 1;
uint32_t rpt4_reserved4:22; /*Reserved.*/
uint32_t reserved24: 8; /*Reserved.*/
};
uint32_t val;
@ -181,19 +183,34 @@ typedef volatile struct efuse_dev_s {
union {
struct {
uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t wafer_version: 3;
uint32_t wafer_version_minor_low: 3;
uint32_t pkg_version: 3;
uint32_t sys_data_part0_0: 8; /*Stores the fist 14 bits of the zeroth part of system data.*/
uint32_t blk_version_minor:3;
uint32_t sys_data_part0_0: 5;
};
uint32_t val;
} rd_mac_spi_sys_3;
uint32_t rd_mac_spi_sys_4; /*BLOCK1 data register $n.*/
uint32_t rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/
union {
struct {
uint32_t reserved1: 23;
uint32_t wafer_version_minor_high: 1;
uint32_t wafer_version_major: 2;
uint32_t reserved2: 6;
};
uint32_t val;
} rd_mac_spi_sys_5; /*BLOCK1 data register $n.*/
uint32_t rd_sys_part1_data0; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data1; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data2; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data3; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/
union {
struct {
uint32_t blk_version_major : 2;
uint32_t reserved1: 30;
};
uint32_t val;
} rd_sys_part1_data4; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data5; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data6; /*Register $n of BLOCK2 (system).*/
uint32_t rd_sys_part1_data7; /*Register $n of BLOCK2 (system).*/

23
components/soc/esp32s2/include/soc/efuse_struct.h
View File

@ -178,7 +178,9 @@ typedef volatile struct efuse_dev_s {
} rd_repeat_data3;
union {
struct {
uint32_t chip_version:24;
uint32_t disable_wafer_version_major: 1;
uint32_t disable_blk_version_major: 1;
uint32_t rpt4_reserved4:22;
uint32_t reserved24: 8;
};
uint32_t val;
@ -201,15 +203,19 @@ typedef volatile struct efuse_dev_s {
union {
struct {
uint32_t spi_pad_conf_2: 18;
uint32_t wafer_version: 3;
uint32_t reserve: 11;
uint32_t wafer_version_major: 2;
uint32_t wafer_version_minor_high: 1; // most significant bit
uint32_t reserve1: 4;
uint32_t blk_version_major: 2;
uint32_t reserve2: 5;
};
uint32_t val;
} rd_mac_spi_8m_3;
union {
struct {
uint32_t pkg_version: 4;
uint32_t reserve: 28;
uint32_t wafer_version_minor_low: 3; // least significant bits
uint32_t reserve: 25;
};
uint32_t val;
} rd_mac_spi_8m_4;
@ -218,7 +224,14 @@ typedef volatile struct efuse_dev_s {
uint32_t rd_sys_data1; /**/
uint32_t rd_sys_data2; /**/
uint32_t rd_sys_data3; /**/
uint32_t rd_sys_data4; /**/
union {
struct {
uint32_t reserved1: 4;
uint32_t blk_version_minor : 3;
uint32_t reserved2: 25;
};
uint32_t val;
} rd_sys_data4; /**/
uint32_t rd_sys_data5; /**/
uint32_t rd_sys_data6; /**/
uint32_t rd_sys_data7; /**/

29
components/soc/esp32s3/include/soc/efuse_struct.h
View File

@ -112,7 +112,9 @@ typedef volatile struct efuse_dev_s {
} rd_repeat_data3;
union {
struct {
uint32_t reg_rpt4_reserved2 : 24; /*Reserved (used for four backups method).*/
uint32_t disable_wafer_version_major : 1;
uint32_t disable_blk_version_major : 1;
uint32_t reg_rpt4_reserved2 : 22; /*Reserved.*/
uint32_t reserved24 : 8; /*Reserved.*/
};
uint32_t val;
@ -128,18 +130,35 @@ typedef volatile struct efuse_dev_s {
uint32_t rd_mac_spi_sys_2;
union {
struct {
uint32_t reg_spi_pad_conf_2 : 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t reg_sys_data_part0_0 : 14; /*Stores the fist 14 bits of the zeroth part of system data.*/
uint32_t spi_pad_conf_2: 18; /*Stores the second part of SPI_PAD_CONF.*/
uint32_t wafer_version_minor_low: 3;
uint32_t pkg_version: 3;
uint32_t blk_version_minor:3;
uint32_t reg_sys_data_part0_0: 5;
};
uint32_t val;
} rd_mac_spi_sys_3;
uint32_t rd_mac_spi_sys_4;
uint32_t rd_mac_spi_sys_5;
union {
struct {
uint32_t reserved1: 23;
uint32_t wafer_version_minor_high: 1;
uint32_t wafer_version_major: 2;
uint32_t reserved2: 6;
};
uint32_t val;
} rd_mac_spi_sys_5;
uint32_t rd_sys_part1_data0;
uint32_t rd_sys_part1_data1;
uint32_t rd_sys_part1_data2;
uint32_t rd_sys_part1_data3;
uint32_t rd_sys_part1_data4;
union {
struct {
uint32_t blk_version_major : 2;
uint32_t reserved1: 30;
};
uint32_t val;
} rd_sys_part1_data4;
uint32_t rd_sys_part1_data5;
uint32_t rd_sys_part1_data6;
uint32_t rd_sys_part1_data7;

2
docs/en/api-reference/system/efuse.rst
View File

@ -276,7 +276,7 @@ Access to the fields is via a pointer to the description structure. API function
* :cpp:func:`esp_efuse_get_keypurpose_dis_write` - Returns a write protection of the key purpose field for an eFuse key block (for esp32 always true).
* :cpp:func:`esp_efuse_key_block_unused` - Returns true if the key block is unused, false otherwise.
For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_chip_ver`, :cpp:func:`esp_efuse_get_pkg_ver`.
For frequently used fields, special functions are made, like this :cpp:func:`esp_efuse_get_pkg_ver`.
.. only:: SOC_EFUSE_KEY_PURPOSE_FIELD or SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY

6
docs/en/migration-guides/system.rst
View File

@ -42,6 +42,7 @@ ESP HW Support
- The header file ``esp_panic.h`` has been deleted. ESP-IDF developers should include ``esp_private/panic_reason.h`` to get supported panic reasons. And should include ``esp_debug_helpers.h`` to use any debug related helper functions, e.g. print backtrace.
- The header file ``soc_log.h`` is now renamed to ``esp_hw_log.h`` and all logging macros have been updated from ``SOC_LOGx`` to ``ESP_HW_LOGx``. ESP-IDF users must use the later form.
- The header files ``spinlock.h``, ``clk_ctrl_os.h`` and ``rtc_wdt.h`` must now be included without the ``soc`` prefix. Eg:- ``#include "spinlock.h"``.
- ``esp_chip_info()`` returns the chip version in the format = 100 * ``major eFuse version`` + ``minor eFuse version``. Thus, the ``revision`` in the ``esp_chip_info_t`` structure is expanded to uint16_t to fit the new format.
PSRAM
^^^^^
@ -92,3 +93,8 @@ Task Watchdog Timers
- Configuration is now passed as a configuration structure.
- The function will now handle subscribing of the idle tasks if configured to do so
Efuse
-----
- Added eFuse wafer revisions: major and minor. The `esp_efuse_get_chip_ver()` API is not compatible with these changes this is why it was removed. Please use instead of it the following APIs: `efuse_hal_get_major_chip_version()`, `efuse_hal_get_minor_chip_version()` or `efuse_hal_chip_revision()`.

2
examples/build_system/cmake/idf_as_lib/stubs/esp32/esp_chip_info.h
View File

@ -17,8 +17,8 @@ extern "C" {
typedef struct {
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint16_t revision; //!< chip revision number (in format MXX; where M - wafer major version, XX - wafer minor version)
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;
void esp_chip_info(esp_chip_info_t *out_info);