From df27a50866250ccb1d7b7d2ecafbe8aca0ae11a6 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Mon, 2 Sep 2019 13:45:18 +0800 Subject: [PATCH 1/2] app_update: re-enable elf-sha256 --- components/esp32/ld/esp32.ld | 14 ++++++++------ components/esp32s2beta/ld/esp32s2beta.ld | 14 ++++++++------ components/esptool_py/project_include.cmake | 2 +- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld index d88cdc0342..e79ca0466f 100644 --- a/components/esp32/ld/esp32.ld +++ b/components/esp32/ld/esp32.ld @@ -43,12 +43,14 @@ MEMORY /* Even though the segment name is iram, it is actually mapped to flash */ - iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18 + iram0_2_seg (RX) : org = 0x400D0020, len = 0x330000-0x20 /* - (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file - which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash - cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).) + (0x20 offset above is a convenience for the app binary image generation. + Flash cache has 64KB pages. The .bin file which is flashed to the chip + has a 0x18 byte file header, and each segment has a 0x08 byte segment + header. Setting this offset makes it simple to meet the flash cache MMU's + constraint that (paddr % 64KB == vaddr % 64KB).) */ @@ -65,9 +67,9 @@ MEMORY len = DRAM0_0_SEG_LEN - CONFIG_BT_RESERVE_DRAM /* Flash mapped constant data */ - drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18 + drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20 - /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */ + /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ /* RTC fast memory (executable). Persists over deep sleep. */ diff --git a/components/esp32s2beta/ld/esp32s2beta.ld b/components/esp32s2beta/ld/esp32s2beta.ld index cc97c4b2fc..54eb54a7bf 100644 --- a/components/esp32s2beta/ld/esp32s2beta.ld +++ b/components/esp32s2beta/ld/esp32s2beta.ld @@ -55,12 +55,14 @@ MEMORY /* Even though the segment name is iram, it is actually mapped to flash */ - iram0_2_seg (RX) : org = 0x40080018, len = 0xb80000-0x18 + iram0_2_seg (RX) : org = 0x40080020, len = 0xb80000-0x20 /* - (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file - which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash - cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).) + (0x20 offset above is a convenience for the app binary image generation. + Flash cache has 64KB pages. The .bin file which is flashed to the chip + has a 0x18 byte file header, and each segment has a 0x08 byte segment + header. Setting this offset makes it simple to meet the flash cache MMU's + constraint that (paddr % 64KB == vaddr % 64KB).) */ @@ -72,9 +74,9 @@ MEMORY dram0_0_seg (RW) : org = DRAM_ORG, len = DRAM_SIZE /* Flash mapped constant data */ - drom0_0_seg (R) : org = 0x3F000018, len = 0x3f0000-0x18 + drom0_0_seg (R) : org = 0x3F000020, len = 0x3f0000-0x20 - /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */ + /* (See iram0_2_seg for meaning of 0x20 offset in the above.) */ /* RTC fast memory (executable). Persists over deep sleep. */ diff --git a/components/esptool_py/project_include.cmake b/components/esptool_py/project_include.cmake index 3c0181cf4d..af78f45836 100644 --- a/components/esptool_py/project_include.cmake +++ b/components/esptool_py/project_include.cmake @@ -43,7 +43,7 @@ string(REPLACE ";" " " ESPTOOLPY_WRITE_FLASH_STR "write_flash ${ESPTOOLPY_FLASH_OPTIONS} ${ESPTOOLPY_EXTRA_FLASH_OPTIONS} ${ESPTOOLPY_COMPRESSED_OPT}") if(NOT BOOTLOADER_BUILD) - # set(ESPTOOLPY_ELF2IMAGE_OPTIONS --elf-sha256-offset 0xb0) + set(ESPTOOLPY_ELF2IMAGE_OPTIONS --elf-sha256-offset 0xb0) endif() if(CONFIG_SECURE_BOOT_ENABLED AND From d7d5aebdeee2e26efabd8c910c68af080a252e40 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Wed, 11 Sep 2019 18:27:10 +0800 Subject: [PATCH 2/2] soc: fix memory map for esp32 and esp32s2beta --- .../soc/esp32s2beta/soc_memory_layout.c | 56 +++++++++---------- components/soc/src/memory_layout_utils.c | 25 ++++++--- 2 files changed, 46 insertions(+), 35 deletions(-) diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c index 38df52df0d..5d6f680ce2 100644 --- a/components/soc/esp32s2beta/soc_memory_layout.c +++ b/components/soc/esp32s2beta/soc_memory_layout.c @@ -44,9 +44,9 @@ const soc_memory_type_desc_t soc_memory_types[] = { // Type 1: DRAM used for startup stacks { "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, true}, //Type 2: DRAM which has an alias on the I-port - //(This DRAM is also the region used by ROM during startup) - { "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true}, + { "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, false}, //Type 3: IRAM + //In ESP32S2beta, All IRAM region are available by D-port (D/IRAM). { "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, //Type 4: SPI SRAM data //TODO, in fact, part of them support EDMA, to be supported. @@ -75,41 +75,41 @@ const soc_memory_region_t soc_memory_regions[] = { #endif #if CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB #if CONFIG_ESP32S2_DATA_CACHE_0KB - { 0x3FFB2000, 0x2000, 0, 0x40022000}, //Block 1, can be use as I/D cache memory - { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory + { 0x3FFB2000, 0x2000, 2, 0x40022000}, //Block 1, can be use as I/D cache memory + { 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory #elif CONFIG_ESP32S2_DATA_CACHE_8KB - { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory + { 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory #else - { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory + { 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory #endif #else #if CONFIG_ESP32S2_DATA_CACHE_0KB - { 0x3FFB4000, 0x2000, 0, 0x40024000}, //Block 2, can be use as D cache memory - { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory + { 0x3FFB4000, 0x2000, 2, 0x40024000}, //Block 2, can be use as D cache memory + { 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory #elif CONFIG_ESP32S2_DATA_CACHE_8KB - { 0x3FFB6000, 0x2000, 0, 0x40026000}, //Block 3, can be use as D cache memory + { 0x3FFB6000, 0x2000, 2, 0x40026000}, //Block 3, can be use as D cache memory #endif #endif - { 0x3FFB8000, 0x4000, 0, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory - { 0x3FFBC000, 0x4000, 0, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory - { 0x3FFC0000, 0x4000, 0, 0x40030000}, //Block 6, can be used as trace memory - { 0x3FFC4000, 0x4000, 0, 0x40034000}, //Block 7, can be used as trace memory - { 0x3FFC8000, 0x4000, 0, 0x40038000}, //Block 8, can be used as trace memory - { 0x3FFCC000, 0x4000, 0, 0x4003C000}, //Block 9, can be used as trace memory + { 0x3FFB8000, 0x4000, 2, 0x40028000}, //Block 4, can be remapped to ROM, can be used as trace memory + { 0x3FFBC000, 0x4000, 2, 0x4002C000}, //Block 5, can be remapped to ROM, can be used as trace memory + { 0x3FFC0000, 0x4000, 2, 0x40030000}, //Block 6, can be used as trace memory + { 0x3FFC4000, 0x4000, 2, 0x40034000}, //Block 7, can be used as trace memory + { 0x3FFC8000, 0x4000, 2, 0x40038000}, //Block 8, can be used as trace memory + { 0x3FFCC000, 0x4000, 2, 0x4003C000}, //Block 9, can be used as trace memory - { 0x3FFD0000, 0x4000, 0, 0x40040000}, //Block 10, can be used as trace memory - { 0x3FFD4000, 0x4000, 0, 0x40044000}, //Block 11, can be used as trace memory - { 0x3FFD8000, 0x4000, 0, 0x40048000}, //Block 12, can be used as trace memory - { 0x3FFDC000, 0x4000, 0, 0x4004C000}, //Block 13, can be used as trace memory - { 0x3FFE0000, 0x4000, 0, 0x40050000}, //Block 14, can be used as trace memory - { 0x3FFE4000, 0x4000, 0, 0x40054000}, //Block 15, can be used as trace memory - { 0x3FFE8000, 0x4000, 0, 0x40058000}, //Block 16, can be used as trace memory - { 0x3FFEC000, 0x4000, 0, 0x4005C000}, //Block 17, can be used as trace memory - { 0x3FFF0000, 0x4000, 0, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory - { 0x3FFF4000, 0x4000, 0, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory - { 0x3FFF8000, 0x4000, 0, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory + { 0x3FFD0000, 0x4000, 2, 0x40040000}, //Block 10, can be used as trace memory + { 0x3FFD4000, 0x4000, 2, 0x40044000}, //Block 11, can be used as trace memory + { 0x3FFD8000, 0x4000, 2, 0x40048000}, //Block 12, can be used as trace memory + { 0x3FFDC000, 0x4000, 2, 0x4004C000}, //Block 13, can be used as trace memory + { 0x3FFE0000, 0x4000, 2, 0x40050000}, //Block 14, can be used as trace memory + { 0x3FFE4000, 0x4000, 2, 0x40054000}, //Block 15, can be used as trace memory + { 0x3FFE8000, 0x4000, 2, 0x40058000}, //Block 16, can be used as trace memory + { 0x3FFEC000, 0x4000, 2, 0x4005C000}, //Block 17, can be used as trace memory + { 0x3FFF0000, 0x4000, 2, 0x40060000}, //Block 18, can be used for MAC dump, can be used as trace memory + { 0x3FFF4000, 0x4000, 2, 0x40064000}, //Block 19, can be used for MAC dump, can be used as trace memory + { 0x3FFF8000, 0x4000, 2, 0x40068000}, //Block 20, can be used for MAC dump, can be used as trace memory { 0x3FFFC000, 0x4000, 1, 0x4006C000}, //Block 21, can be used for MAC dump, can be used as trace memory, used for startup stack }; diff --git a/components/soc/src/memory_layout_utils.c b/components/soc/src/memory_layout_utils.c index cc3b91046f..6f7f690bfb 100644 --- a/components/soc/src/memory_layout_utils.c +++ b/components/soc/src/memory_layout_utils.c @@ -15,6 +15,7 @@ #include #include "esp_log.h" #include "soc/soc_memory_layout.h" +#include "sdkconfig.h" static const char *TAG = "memory_layout"; @@ -69,8 +70,19 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c /* Add the EXTRA_RESERVED_REGIONS at the beginning */ reserved[0].start = (intptr_t)&_data_start; /* DRAM used by data+bss */ reserved[0].end = (intptr_t)&_static_data_end; +#if CONFIG_IDF_TARGET_ESP32 + //ESP32 has a IRAM-only region 0x4008_0000 - 0x4009_FFFF, protect the used part reserved[1].start = (intptr_t)&_iram_start; /* IRAM used by code */ reserved[1].end = (intptr_t)&_iram_end; +#elif CONFIG_IDF_TARGET_ESP32S2BETA + //ESP32S2 has a big D/IRAM region, the part used by code is reserved + //The address of the D/I bus are in the same order, directly shift IRAM address to get reserved DRAM address + const uint32_t i_d_offset = SOC_IRAM_LOW - SOC_DRAM_LOW; + reserved[1].start = (intptr_t)&_iram_start - i_d_offset; /* IRAM used by code */ + reserved[1].end = (intptr_t)&_iram_end - i_d_offset; +#else +# error chip not implemented! +#endif /* Sort by starting address */ qsort(reserved, count, sizeof(soc_reserved_region_t), s_compare_reserved_regions); @@ -127,15 +139,14 @@ size_t soc_get_available_memory_regions(soc_memory_region_t *regions) bool move_to_next = true; for (size_t i = 0; i < num_reserved; i++) { - if (reserved[i].start >= SOC_DRAM_HIGH && in_end < SOC_DRAM_HIGH && in.iram_address != 0) { - reserved[i].start = reserved[i].start - (in.iram_address - in.start); - reserved[i].end = reserved[i].end - (in.iram_address - in.start); - } - - if (reserved[i].end <= in_start || reserved[i].start >= in_end) { - /* reserved region ends before 'in' starts or reserved region starts after 'in' ends */ + if (reserved[i].end <= in_start) { + /* reserved region ends before 'in' starts */ continue; } + else if (reserved[i].start >= in_end) { + /* reserved region starts after 'in' ends */ + break; + } else if (reserved[i].start <= in_start && reserved[i].end >= in_end) { /* reserved covers all of 'in' */ ESP_EARLY_LOGV(TAG, "Region 0x%08x - 0x%08x inside of reserved 0x%08x - 0x%08x",