From 0e904b3f7e5535a711bc310a6aa1b03c68906323 Mon Sep 17 00:00:00 2001
From: Renz Bagaporo <renz.bagaporo@espressif.com>
Date: Wed, 24 Mar 2021 19:58:12 +0800
Subject: [PATCH] ulp: clear rtc int at initialization

Closes https://github.com/espressif/esp-idf/issues/6654
---
 components/bootloader_support/src/bootloader_clock_init.c | 3 +++
 components/esp_common/src/brownout.c                      | 1 +
 components/esp_hw_support/port/esp32/rtc_init.c           | 3 +++
 components/esp_hw_support/port/esp32c3/rtc_init.c         | 3 +++
 components/esp_hw_support/port/esp32s2/rtc_init.c         | 3 +++
 components/esp_hw_support/port/esp32s3/rtc_init.c         | 3 +++
 6 files changed, 16 insertions(+)

diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c
index db1a736d12..dee8bf201b 100644
--- a/components/bootloader_support/src/bootloader_clock_init.c
+++ b/components/bootloader_support/src/bootloader_clock_init.c
@@ -80,4 +80,7 @@ __attribute__((weak)) void bootloader_clock_configure(void)
         rtc_clk_32k_bootstrap(CONFIG_ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES);
     }
 #endif // CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
+
+    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
+    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
 }
diff --git a/components/esp_common/src/brownout.c b/components/esp_common/src/brownout.c
index 91eea5eecc..f65d31de5e 100644
--- a/components/esp_common/src/brownout.c
+++ b/components/esp_common/src/brownout.c
@@ -79,6 +79,7 @@ void esp_brownout_init(void)
 
     brownout_hal_config(&cfg);
 
+
 #ifndef SOC_BROWNOUT_RESET_SUPPORTED
     rtc_isr_register(rtc_brownout_isr_handler, NULL, RTC_CNTL_BROWN_OUT_INT_ENA_M);
 
diff --git a/components/esp_hw_support/port/esp32/rtc_init.c b/components/esp_hw_support/port/esp32/rtc_init.c
index 9b2911d42d..f86811a99f 100644
--- a/components/esp_hw_support/port/esp32/rtc_init.c
+++ b/components/esp_hw_support/port/esp32/rtc_init.c
@@ -96,6 +96,9 @@ void rtc_init(rtc_config_t cfg)
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
     }
+
+    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
+    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32c3/rtc_init.c b/components/esp_hw_support/port/esp32c3/rtc_init.c
index 8697388969..2cadbbabd0 100644
--- a/components/esp_hw_support/port/esp32c3/rtc_init.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_init.c
@@ -151,6 +151,9 @@ void rtc_init(rtc_config_t cfg)
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
         CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
     }
+
+    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
+    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32s2/rtc_init.c b/components/esp_hw_support/port/esp32s2/rtc_init.c
index 85c3b21748..cd212bdeb3 100644
--- a/components/esp_hw_support/port/esp32s2/rtc_init.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_init.c
@@ -159,6 +159,9 @@ void rtc_init(rtc_config_t cfg)
             calibrate_ocode();
         }
     }
+
+    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
+    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
diff --git a/components/esp_hw_support/port/esp32s3/rtc_init.c b/components/esp_hw_support/port/esp32s3/rtc_init.c
index 96f36cac97..0662c6b757 100644
--- a/components/esp_hw_support/port/esp32s3/rtc_init.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_init.c
@@ -189,6 +189,9 @@ void rtc_init(rtc_config_t cfg)
         }
         rtc_clk_cpu_freq_set_config(&old_config);
     }
+
+    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
+    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
 }
 
 rtc_vddsdio_config_t rtc_vddsdio_get_config(void)