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https://github.com/espressif/esp-idf.git
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Merge branch 'bugfix/fix_spi_hd_quad_issue_esp32c3' into 'master'
essl_spi: fix wrong dummy cycle under quad spi mode ant add a test to verify spi quad mod Closes IDF-5182 and IDF-5181 See merge request espressif/esp-idf!18680
This commit is contained in:
Gao Xu
commit
0da21aca0d
@ -990,6 +990,31 @@ UT_S2_SPI_DUAL:
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- ESP32S2_IDF
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- ESP32S2_IDF
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- Example_SPI_Multi_device
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- Example_SPI_Multi_device
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UT_S2_SPI_QUAD:
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extends: .unit_test_esp32s2_template
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tags:
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- ESP32S2_IDF
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- Example_SPI_Quad_Multi_device
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UT_S3_SPI_QUAD:
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extends: .unit_test_esp32s3_template
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tags:
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- ESP32S3_IDF
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- Example_SPI_Quad_Multi_device
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UT_C2_SPI_QUAD:
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extends: .unit_test_esp32c2_template
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tags:
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- ESP32C2_IDF
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- Example_SPI_Quad_Multi_device
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- xtal_40mhz
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UT_C3_SPI_QUAD:
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extends: .unit_test_esp32c3_template
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tags:
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- ESP32C3_IDF
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- Example_SPI_Quad_Multi_device
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UT_S2_SDSPI:
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UT_S2_SDSPI:
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extends: .unit_test_esp32s2_template
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extends: .unit_test_esp32s2_template
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tags:
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tags:
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@ -298,6 +298,13 @@ void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev,
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/**
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/**
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* This function is used to get tx_buffer used in dual-board test
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* This function is used to get tx_buffer used in dual-board test
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* `master_send_buf` and `slave_send_buf` will be fulfilled with same random numbers with the seed of `seed`.
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*
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* @param seed Random number seed
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* @param master_send_buf Master TX buffer
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* @param slave_send_buf Slave TX buffer
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* @param send_buf_size Buffer size
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*/
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*/
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void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size);
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void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_buf, int send_buf_size);
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#endif //_TEST_COMMON_SPI_H_
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#endif //_TEST_COMMON_SPI_H_
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@ -245,7 +245,7 @@ void get_tx_buffer(uint32_t seed, uint8_t *master_send_buf, uint8_t *slave_send_
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{
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{
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srand(seed);
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srand(seed);
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for (int i = 0; i < send_buf_size; i++) {
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for (int i = 0; i < send_buf_size; i++) {
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slave_send_buf[i] = rand();
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slave_send_buf[i] = rand() % 256;
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master_send_buf[i] = rand();
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master_send_buf[i] = rand() % 256;
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}
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}
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}
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}
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@ -16,16 +16,14 @@
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#include "soc/spi_periph.h"
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#include "soc/spi_periph.h"
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#include "driver/spi_master.h"
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#include "driver/spi_master.h"
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#include "esp_serial_slave_link/essl_spi.h"
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#include "esp_serial_slave_link/essl_spi.h"
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#include "test/test_common_spi.h"
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#if (TEST_SPI_PERIPH_NUM >= 2)
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//These will be only enabled on chips with 2 or more SPI peripherals
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#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#include "driver/spi_slave_hd.h"
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#include "driver/spi_slave_hd.h"
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#if (TEST_SPI_PERIPH_NUM >= 2) //These will be only enabled on chips with 2 or more SPI peripherals
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#include "esp_rom_gpio.h"
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#include "esp_rom_gpio.h"
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#include "unity.h"
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#include "test/test_common_spi.h"
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#define TEST_DMA_MAX_SIZE 4092
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#define TEST_DMA_MAX_SIZE 4092
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#define TEST_BUFFER_SIZE 256 ///< buffer size of each wrdma buffer in fifo mode
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#define TEST_BUFFER_SIZE 256 ///< buffer size of each wrdma buffer in fifo mode
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@ -57,7 +55,6 @@ typedef struct {
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spi_slave_hd_data_t rx_data;
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spi_slave_hd_data_t rx_data;
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} testhd_context_t;
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} testhd_context_t;
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static uint32_t get_hd_flags(void)
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static uint32_t get_hd_flags(void)
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{
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{
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#if !defined(SLAVE_SUPPORT_QIO)
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#if !defined(SLAVE_SUPPORT_QIO)
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@ -595,13 +592,9 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
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master_free_device_bus(spi);
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master_free_device_bus(spi);
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}
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}
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#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#endif //#if (TEST_SPI_PERIPH_NUM >= 2)
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#endif //#if (TEST_SPI_PERIPH_NUM >= 2)
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#if (TEST_SPI_PERIPH_NUM == 1)
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#if (TEST_SPI_PERIPH_NUM == 1)
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#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C2)
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//These tests are for chips which only have 1 SPI controller
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//These tests are for chips which only have 1 SPI controller
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/********************************************************************************
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/********************************************************************************
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* Test By Master & Slave (2 boards)
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* Test By Master & Slave (2 boards)
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@ -616,9 +609,6 @@ TEST_CASE("test spi slave hd segment mode, master too long", "[spi][spi_slv_hd]"
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* GND | GND | GND |
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* GND | GND | GND |
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*
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*
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********************************************************************************/
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********************************************************************************/
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#include "driver/spi_slave_hd.h"
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#include "unity.h"
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#include "test/test_common_spi.h"
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static void hd_master(void)
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static void hd_master(void)
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{
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{
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@ -749,6 +739,148 @@ static void hd_slave(void)
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}
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}
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TEST_CASE_MULTIPLE_DEVICES("SPI Slave HD: segment mode, master sends too long", "[spi_ms][test_env=Example_SPI_Multi_device]", hd_master, hd_slave);
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TEST_CASE_MULTIPLE_DEVICES("SPI Slave HD: segment mode, master sends too long", "[spi_ms][test_env=Example_SPI_Multi_device]", hd_master, hd_slave);
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#endif //!TEMPORARY_DISABLED_FOR_TARGETS(...)
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#endif //#if SOC_SPI_SUPPORT_SLAVE_HD_VER2
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#endif //#if (TEST_SPI_PERIPH_NUM == 1)
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#endif //#if (TEST_SPI_PERIPH_NUM == 1)
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/**
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* TODO IDF-5483
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**/
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#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
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#define BUF_SIZE 256
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static void hd_master_quad(void){
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spi_bus_config_t bus_cfg = {
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.miso_io_num = PIN_NUM_MISO,
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.mosi_io_num = PIN_NUM_MOSI,
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.sclk_io_num = PIN_NUM_CLK,
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.quadwp_io_num = PIN_NUM_WP,
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.quadhd_io_num = PIN_NUM_HD
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};
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TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &bus_cfg, SPI_DMA_CH_AUTO));
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spi_device_handle_t spi;
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spi_device_interface_config_t dev_cfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
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dev_cfg.flags = SPI_DEVICE_HALFDUPLEX;
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dev_cfg.command_bits = 8;
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dev_cfg.address_bits = 8;
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dev_cfg.dummy_bits = 8;
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dev_cfg.clock_speed_hz = 100 * 1000;
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TEST_ESP_OK(spi_bus_add_device(TEST_SPI_HOST, &dev_cfg, &spi));
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WORD_ALIGNED_ATTR uint8_t *master_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA);
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WORD_ALIGNED_ATTR uint8_t *master_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA);
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//This buffer is used for 2-board test and should be assigned totally the same as the ``hd_slave`` does.
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WORD_ALIGNED_ATTR uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA);
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get_tx_buffer(199, master_send_buf, slave_send_buf, BUF_SIZE);
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unity_wait_for_signal("slave ready");
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essl_spi_wrdma(spi, master_send_buf, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO);
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unity_wait_for_signal("slave ready");
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essl_spi_wrdma(spi, master_send_buf + BUF_SIZE / 2, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO);
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unity_wait_for_signal("slave ready");
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essl_spi_rddma(spi, master_recv_buf, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO);
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unity_wait_for_signal("slave ready");
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essl_spi_rddma(spi, master_recv_buf+ BUF_SIZE / 2, BUF_SIZE / 2, -1, SPI_TRANS_MODE_QIO);
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ESP_LOG_BUFFER_HEX("slave send", slave_send_buf, BUF_SIZE);
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ESP_LOG_BUFFER_HEX("master recv", master_recv_buf, BUF_SIZE);
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TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_send_buf, master_recv_buf, BUF_SIZE);
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free(master_recv_buf);
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free(master_send_buf);
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free(slave_send_buf);
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master_free_device_bus(spi);
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}
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static void hd_slave_quad(void){
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spi_bus_config_t bus_cfg = {
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.miso_io_num = PIN_NUM_MISO,
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.mosi_io_num = PIN_NUM_MOSI,
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.sclk_io_num = PIN_NUM_CLK,
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.quadwp_io_num = PIN_NUM_WP,
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.quadhd_io_num = PIN_NUM_HD,
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.max_transfer_sz = 14000 * 30
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};
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spi_slave_hd_slot_config_t slave_hd_cfg = {
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.spics_io_num = PIN_NUM_CS,
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.dma_chan = SPI_DMA_CH_AUTO,
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.flags = 0,
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.mode = 0,
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.command_bits = 8,
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.address_bits = 8,
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.dummy_bits = 8,
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.queue_size = 10,
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};
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TEST_ESP_OK(spi_slave_hd_init(TEST_SLAVE_HOST, &bus_cfg, &slave_hd_cfg));
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WORD_ALIGNED_ATTR uint8_t *slave_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA);
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WORD_ALIGNED_ATTR uint8_t *slave_recv_buf = heap_caps_calloc(BUF_SIZE, 1, MALLOC_CAP_DMA);
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//This buffer is used for 2-board test and should be assigned totally the same as the ``hd_master`` does.
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WORD_ALIGNED_ATTR uint8_t *master_send_buf = heap_caps_malloc(BUF_SIZE, MALLOC_CAP_DMA);
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get_tx_buffer(199, master_send_buf, slave_send_buf, BUF_SIZE);
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int trans_len = BUF_SIZE / 2;
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spi_slave_hd_data_t slave_trans[4] = {
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//recv, the buffer size should be aligned to 4
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{
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.data = slave_recv_buf,
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.len = (trans_len + 3) & (~3),
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},
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{
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.data = slave_recv_buf+BUF_SIZE/2,
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.len = (trans_len + 3) & (~3),
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},
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//send
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{
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.data = slave_send_buf,
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.len = (trans_len + 3) & (~3),
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|
},
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|
{
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|
.data = slave_send_buf+BUF_SIZE/2,
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|
.len = (trans_len + 3) & (~3),
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|
},
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|
};
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|
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|
for (int i = 0; i < 2; i ++) {
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|
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &slave_trans[i], portMAX_DELAY));
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|
unity_send_signal("slave ready");
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|
}
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|
for (int i = 2; i < 4; i ++) {
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|
TEST_ESP_OK(spi_slave_hd_queue_trans(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &slave_trans[i], portMAX_DELAY));
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|
unity_send_signal("slave ready");
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|
}
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|
for (int i = 0; i < 2; i ++) {
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|
spi_slave_hd_data_t *ret_trans;
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|
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_RX, &ret_trans, portMAX_DELAY));
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|
}
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|
for (int i = 2; i < 4; i ++) {
|
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|
spi_slave_hd_data_t *ret_trans;
|
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|
TEST_ESP_OK(spi_slave_hd_get_trans_res(TEST_SLAVE_HOST, SPI_SLAVE_CHAN_TX, &ret_trans, portMAX_DELAY));
|
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|
}
|
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|
|
||||||
|
ESP_LOG_BUFFER_HEX("master send", master_send_buf, BUF_SIZE);
|
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|
ESP_LOG_BUFFER_HEX("slave recv", slave_recv_buf, BUF_SIZE);
|
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|
|
||||||
|
TEST_ASSERT_EQUAL_HEX8_ARRAY(master_send_buf, slave_recv_buf, BUF_SIZE);
|
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|
|
||||||
|
free(slave_recv_buf);
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|
free(slave_send_buf);
|
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|
free(master_send_buf);
|
||||||
|
|
||||||
|
spi_slave_hd_deinit(TEST_SLAVE_HOST);
|
||||||
|
}
|
||||||
|
|
||||||
|
TEST_CASE_MULTIPLE_DEVICES("SPI quad hd test ", "[spi_ms][test_env=Example_SPI_Quad_Multi_device]", hd_master_quad, hd_slave_quad);
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||||||
|
|
||||||
|
#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
|
||||||
|
|
||||||
|
#endif //SOC_SPI_SUPPORT_SLAVE_HD_VER2
|
||||||
|
|||||||
@ -13,8 +13,8 @@
|
|||||||
#include "esp_private/periph_ctrl.h"
|
#include "esp_private/periph_ctrl.h"
|
||||||
#include "essl_internal.h"
|
#include "essl_internal.h"
|
||||||
#include "essl_spi.h"
|
#include "essl_spi.h"
|
||||||
#include "essl_spi/esp32s2_defs.h"
|
#include "hal/spi_types.h"
|
||||||
|
#include "hal/spi_ll.h"
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Initialise device function list of SPI by this macro.
|
* Initialise device function list of SPI by this macro.
|
||||||
@ -51,51 +51,54 @@ typedef struct {
|
|||||||
} master_in;
|
} master_in;
|
||||||
} essl_spi_context_t;
|
} essl_spi_context_t;
|
||||||
|
|
||||||
|
static uint16_t get_hd_command(spi_command_t cmd_t, uint32_t flags)
|
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static uint16_t get_hd_command(uint16_t cmd_i, uint32_t flags)
|
|
||||||
{
|
{
|
||||||
//have no prefixes
|
spi_line_mode_t line_mode = {
|
||||||
if (cmd_i == CMD_HD_EN_QPI_REG) return cmd_i;
|
.cmd_lines = 1,
|
||||||
//doesn't support 4-line commands
|
};
|
||||||
if(flags & SPI_TRANS_MODE_QIO && flags & SPI_TRANS_MODE_DIOQIO_ADDR &&
|
|
||||||
(cmd_i == CMD_HD_WR_END_REG || cmd_i == CMD_HD_INT0_REG ||
|
|
||||||
cmd_i == CMD_HD_INT1_REG || cmd_i == CMD_HD_INT2_REG)) {
|
|
||||||
//the transaction will be sent in corresponding 1/2/4 bit mode, without address and data.
|
|
||||||
//the CMD will have no 0xA- prefix
|
|
||||||
return cmd_i;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (flags & SPI_TRANS_MODE_DIO) {
|
if (flags & SPI_TRANS_MODE_DIO) {
|
||||||
|
line_mode.data_lines = 2;
|
||||||
if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
|
if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
|
||||||
return cmd_i | CMD_HD_DIO_MODE;
|
line_mode.addr_lines = 2;
|
||||||
} else {
|
} else {
|
||||||
return cmd_i | CMD_HD_DOUT_MODE;
|
line_mode.addr_lines = 1;
|
||||||
}
|
}
|
||||||
} else if (flags & SPI_TRANS_MODE_QIO) {
|
} else if (flags & SPI_TRANS_MODE_QIO) {
|
||||||
|
line_mode.data_lines = 4;
|
||||||
if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
|
if (flags & SPI_TRANS_MODE_DIOQIO_ADDR) {
|
||||||
return cmd_i | CMD_HD_QIO_MODE;
|
line_mode.addr_lines = 4;
|
||||||
} else {
|
} else {
|
||||||
return cmd_i | CMD_HD_QOUT_MODE;
|
line_mode.addr_lines = 1;
|
||||||
}
|
}
|
||||||
|
} else {
|
||||||
|
line_mode.data_lines = 1;
|
||||||
|
line_mode.addr_lines = 1;
|
||||||
}
|
}
|
||||||
return cmd_i | CMD_HD_ONEBIT_MODE;
|
|
||||||
|
return spi_ll_get_slave_hd_command(cmd_t, line_mode);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int get_hd_dummy_bits(uint32_t flags)
|
static int get_hd_dummy_bits(uint32_t flags)
|
||||||
{
|
{
|
||||||
//dummy is always 4 cycles when dual or quad mode is enabled. Otherwise 8 cycles in normal mode.
|
spi_line_mode_t line_mode = {};
|
||||||
if (flags & (SPI_TRANS_MODE_DIO | SPI_TRANS_MODE_QIO)) {
|
|
||||||
return 4;
|
if (flags & SPI_TRANS_MODE_DIO) {
|
||||||
|
line_mode.data_lines = 2;
|
||||||
|
} else if (flags & SPI_TRANS_MODE_QIO) {
|
||||||
|
line_mode.data_lines = 4;
|
||||||
} else {
|
} else {
|
||||||
return 8;
|
line_mode.data_lines = 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
return spi_ll_get_slave_hd_dummy_bits(line_mode);
|
||||||
}
|
}
|
||||||
|
|
||||||
esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags)
|
esp_err_t essl_spi_rdbuf(spi_device_handle_t spi, uint8_t *out_data, int addr, int len, uint32_t flags)
|
||||||
{
|
{
|
||||||
spi_transaction_ext_t t = {
|
spi_transaction_ext_t t = {
|
||||||
.base = {
|
.base = {
|
||||||
.cmd = get_hd_command(CMD_HD_RDBUF_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags),
|
||||||
.addr = addr % 72,
|
.addr = addr % 72,
|
||||||
.rxlength = len * 8,
|
.rxlength = len * 8,
|
||||||
.rx_buffer = out_data,
|
.rx_buffer = out_data,
|
||||||
@ -111,7 +114,7 @@ esp_err_t essl_spi_rdbuf_polling(spi_device_handle_t spi, uint8_t *out_data, int
|
|||||||
{
|
{
|
||||||
spi_transaction_ext_t t = {
|
spi_transaction_ext_t t = {
|
||||||
.base = {
|
.base = {
|
||||||
.cmd = get_hd_command(CMD_HD_RDBUF_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_RDBUF, flags),
|
||||||
.addr = addr % 72,
|
.addr = addr % 72,
|
||||||
.rxlength = len * 8,
|
.rxlength = len * 8,
|
||||||
.rx_buffer = out_data,
|
.rx_buffer = out_data,
|
||||||
@ -127,7 +130,7 @@ esp_err_t essl_spi_wrbuf(spi_device_handle_t spi, const uint8_t *data, int addr,
|
|||||||
{
|
{
|
||||||
spi_transaction_ext_t t = {
|
spi_transaction_ext_t t = {
|
||||||
.base = {
|
.base = {
|
||||||
.cmd = get_hd_command(CMD_HD_WRBUF_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags),
|
||||||
.addr = addr % 72,
|
.addr = addr % 72,
|
||||||
.length = len * 8,
|
.length = len * 8,
|
||||||
.tx_buffer = data,
|
.tx_buffer = data,
|
||||||
@ -142,7 +145,7 @@ esp_err_t essl_spi_wrbuf_polling(spi_device_handle_t spi, const uint8_t *data, i
|
|||||||
{
|
{
|
||||||
spi_transaction_ext_t t = {
|
spi_transaction_ext_t t = {
|
||||||
.base = {
|
.base = {
|
||||||
.cmd = get_hd_command(CMD_HD_WRBUF_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_WRBUF, flags),
|
||||||
.addr = addr % 72,
|
.addr = addr % 72,
|
||||||
.length = len * 8,
|
.length = len * 8,
|
||||||
.tx_buffer = data,
|
.tx_buffer = data,
|
||||||
@ -157,7 +160,7 @@ esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg
|
|||||||
{
|
{
|
||||||
spi_transaction_ext_t t = {
|
spi_transaction_ext_t t = {
|
||||||
.base = {
|
.base = {
|
||||||
.cmd = get_hd_command(CMD_HD_RDDMA_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_RDDMA, flags),
|
||||||
.rxlength = seg_len * 8,
|
.rxlength = seg_len * 8,
|
||||||
.rx_buffer = out_data,
|
.rx_buffer = out_data,
|
||||||
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
|
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
|
||||||
@ -170,7 +173,7 @@ esp_err_t essl_spi_rddma_seg(spi_device_handle_t spi, uint8_t *out_data, int seg
|
|||||||
esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags)
|
esp_err_t essl_spi_rddma_done(spi_device_handle_t spi, uint32_t flags)
|
||||||
{
|
{
|
||||||
spi_transaction_t end_t = {
|
spi_transaction_t end_t = {
|
||||||
.cmd = get_hd_command(CMD_HD_INT0_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_INT0, flags),
|
||||||
.flags = flags,
|
.flags = flags,
|
||||||
};
|
};
|
||||||
return spi_device_transmit(spi, &end_t);
|
return spi_device_transmit(spi, &end_t);
|
||||||
@ -201,7 +204,7 @@ esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int s
|
|||||||
{
|
{
|
||||||
spi_transaction_ext_t t = {
|
spi_transaction_ext_t t = {
|
||||||
.base = {
|
.base = {
|
||||||
.cmd = get_hd_command(CMD_HD_WRDMA_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_WRDMA, flags),
|
||||||
.length = seg_len * 8,
|
.length = seg_len * 8,
|
||||||
.tx_buffer = data,
|
.tx_buffer = data,
|
||||||
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
|
.flags = flags | SPI_TRANS_VARIABLE_DUMMY,
|
||||||
@ -214,7 +217,7 @@ esp_err_t essl_spi_wrdma_seg(spi_device_handle_t spi, const uint8_t *data, int s
|
|||||||
esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags)
|
esp_err_t essl_spi_wrdma_done(spi_device_handle_t spi, uint32_t flags)
|
||||||
{
|
{
|
||||||
spi_transaction_t end_t = {
|
spi_transaction_t end_t = {
|
||||||
.cmd = get_hd_command(CMD_HD_WR_END_REG, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_WR_END, flags),
|
||||||
.flags = flags,
|
.flags = flags,
|
||||||
};
|
};
|
||||||
return spi_device_transmit(spi, &end_t);
|
return spi_device_transmit(spi, &end_t);
|
||||||
@ -243,7 +246,7 @@ esp_err_t essl_spi_wrdma(spi_device_handle_t spi, const uint8_t *data, int len,
|
|||||||
esp_err_t essl_spi_int(spi_device_handle_t spi, int int_n, uint32_t flags)
|
esp_err_t essl_spi_int(spi_device_handle_t spi, int int_n, uint32_t flags)
|
||||||
{
|
{
|
||||||
spi_transaction_t end_t = {
|
spi_transaction_t end_t = {
|
||||||
.cmd = get_hd_command(CMD_HD_INT0_REG + int_n, flags),
|
.cmd = get_hd_command(SPI_CMD_HD_INT0 + int_n, flags),
|
||||||
.flags = flags,
|
.flags = flags,
|
||||||
};
|
};
|
||||||
return spi_device_transmit(spi, &end_t);
|
return spi_device_transmit(spi, &end_t);
|
||||||
|
|||||||
@ -1,30 +0,0 @@
|
|||||||
/*
|
|
||||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#pragma once
|
|
||||||
|
|
||||||
// NOTE: From the view of master
|
|
||||||
#define CMD_HD_WRBUF_REG 0x01
|
|
||||||
#define CMD_HD_RDBUF_REG 0x02
|
|
||||||
#define CMD_HD_WRDMA_REG 0x03
|
|
||||||
#define CMD_HD_RDDMA_REG 0x04
|
|
||||||
|
|
||||||
#define CMD_HD_ONEBIT_MODE 0x00
|
|
||||||
#define CMD_HD_DOUT_MODE 0x10
|
|
||||||
#define CMD_HD_QOUT_MODE 0x20
|
|
||||||
#define CMD_HD_DIO_MODE 0x50
|
|
||||||
#define CMD_HD_QIO_MODE 0xA0
|
|
||||||
|
|
||||||
#define CMD_HD_SEG_END_REG 0x05
|
|
||||||
#define CMD_HD_EN_QPI_REG 0x06
|
|
||||||
#define CMD_HD_WR_END_REG 0x07
|
|
||||||
#define CMD_HD_INT0_REG 0x08
|
|
||||||
#define CMD_HD_INT1_REG 0x09
|
|
||||||
#define CMD_HD_INT2_REG 0x0A
|
|
||||||
#define CMD_HD_EX_QPI_REG 0xDD
|
|
||||||
|
|
||||||
#define SPI_SLAVE_HD_BUFFER_SIZE 64
|
|
||||||
@ -1,38 +0,0 @@
|
|||||||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
|
|
||||||
|
|
||||||
#pragma once
|
|
||||||
|
|
||||||
// NOTE: From the view of master
|
|
||||||
#define CMD_HD_WRBUF_REG 0x01
|
|
||||||
#define CMD_HD_RDBUF_REG 0x02
|
|
||||||
#define CMD_HD_WRDMA_REG 0x03
|
|
||||||
#define CMD_HD_RDDMA_REG 0x04
|
|
||||||
|
|
||||||
#define CMD_HD_ONEBIT_MODE 0x00
|
|
||||||
#define CMD_HD_DOUT_MODE 0x10
|
|
||||||
#define CMD_HD_QOUT_MODE 0x20
|
|
||||||
#define CMD_HD_DIO_MODE 0x50
|
|
||||||
#define CMD_HD_QIO_MODE 0xA0
|
|
||||||
|
|
||||||
#define CMD_HD_SEG_END_REG 0x05
|
|
||||||
#define CMD_HD_EN_QPI_REG 0x06
|
|
||||||
#define CMD_HD_WR_END_REG 0x07
|
|
||||||
#define CMD_HD_INT0_REG 0x08
|
|
||||||
#define CMD_HD_INT1_REG 0x09
|
|
||||||
#define CMD_HD_INT2_REG 0x0A
|
|
||||||
#define CMD_HD_EX_QPI_REG 0xDD
|
|
||||||
|
|
||||||
#define SPI_SLAVE_HD_BUFFER_SIZE 64
|
|
||||||
@ -1,30 +0,0 @@
|
|||||||
/*
|
|
||||||
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#pragma once
|
|
||||||
|
|
||||||
// NOTE: From the view of master
|
|
||||||
#define CMD_HD_WRBUF_REG 0x01
|
|
||||||
#define CMD_HD_RDBUF_REG 0x02
|
|
||||||
#define CMD_HD_WRDMA_REG 0x03
|
|
||||||
#define CMD_HD_RDDMA_REG 0x04
|
|
||||||
|
|
||||||
#define CMD_HD_ONEBIT_MODE 0x00
|
|
||||||
#define CMD_HD_DOUT_MODE 0x10
|
|
||||||
#define CMD_HD_QOUT_MODE 0x20
|
|
||||||
#define CMD_HD_DIO_MODE 0x50
|
|
||||||
#define CMD_HD_QIO_MODE 0xA0
|
|
||||||
|
|
||||||
#define CMD_HD_SEG_END_REG 0x05
|
|
||||||
#define CMD_HD_EN_QPI_REG 0x06
|
|
||||||
#define CMD_HD_WR_END_REG 0x07
|
|
||||||
#define CMD_HD_INT0_REG 0x08
|
|
||||||
#define CMD_HD_INT1_REG 0x09
|
|
||||||
#define CMD_HD_INT2_REG 0x0A
|
|
||||||
#define CMD_HD_EX_QPI_REG 0xDD
|
|
||||||
|
|
||||||
#define SPI_SLAVE_HD_BUFFER_SIZE 64
|
|
||||||
@ -1,38 +0,0 @@
|
|||||||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
|
|
||||||
|
|
||||||
#pragma once
|
|
||||||
|
|
||||||
// NOTE: From the view of master
|
|
||||||
#define CMD_HD_WRBUF_REG 0x01
|
|
||||||
#define CMD_HD_RDBUF_REG 0x02
|
|
||||||
#define CMD_HD_WRDMA_REG 0x03
|
|
||||||
#define CMD_HD_RDDMA_REG 0x04
|
|
||||||
|
|
||||||
#define CMD_HD_ONEBIT_MODE 0x00
|
|
||||||
#define CMD_HD_DOUT_MODE 0x10
|
|
||||||
#define CMD_HD_QOUT_MODE 0x20
|
|
||||||
#define CMD_HD_DIO_MODE 0x50
|
|
||||||
#define CMD_HD_QIO_MODE 0xA0
|
|
||||||
|
|
||||||
#define CMD_HD_SEG_END_REG 0x05
|
|
||||||
#define CMD_HD_EN_QPI_REG 0x06
|
|
||||||
#define CMD_HD_WR_END_REG 0x07
|
|
||||||
#define CMD_HD_INT0_REG 0x08
|
|
||||||
#define CMD_HD_INT1_REG 0x09
|
|
||||||
#define CMD_HD_INT2_REG 0x0A
|
|
||||||
#define CMD_HD_EX_QPI_REG 0xDD
|
|
||||||
|
|
||||||
#define SPI_SLAVE_HD_BUFFER_SIZE 72
|
|
||||||
@ -1,38 +0,0 @@
|
|||||||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
|
||||||
//
|
|
||||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
|
||||||
// you may not use this file except in compliance with the License.
|
|
||||||
// You may obtain a copy of the License at
|
|
||||||
//
|
|
||||||
// http://www.apache.org/licenses/LICENSE-2.0
|
|
||||||
//
|
|
||||||
// Unless required by applicable law or agreed to in writing, software
|
|
||||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
|
||||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
||||||
// See the License for the specific language governing permissions and
|
|
||||||
// limitations under the License.
|
|
||||||
|
|
||||||
|
|
||||||
#pragma once
|
|
||||||
|
|
||||||
// NOTE: From the view of master
|
|
||||||
#define CMD_HD_WRBUF_REG 0x01
|
|
||||||
#define CMD_HD_RDBUF_REG 0x02
|
|
||||||
#define CMD_HD_WRDMA_REG 0x03
|
|
||||||
#define CMD_HD_RDDMA_REG 0x04
|
|
||||||
|
|
||||||
#define CMD_HD_ONEBIT_MODE 0x00
|
|
||||||
#define CMD_HD_DOUT_MODE 0x10
|
|
||||||
#define CMD_HD_QOUT_MODE 0x20
|
|
||||||
#define CMD_HD_DIO_MODE 0x50
|
|
||||||
#define CMD_HD_QIO_MODE 0xA0
|
|
||||||
|
|
||||||
#define CMD_HD_SEG_END_REG 0x05
|
|
||||||
#define CMD_HD_EN_QPI_REG 0x06
|
|
||||||
#define CMD_HD_WR_END_REG 0x07
|
|
||||||
#define CMD_HD_INT0_REG 0x08
|
|
||||||
#define CMD_HD_INT1_REG 0x09
|
|
||||||
#define CMD_HD_INT2_REG 0x0A
|
|
||||||
#define CMD_HD_EX_QPI_REG 0xDD
|
|
||||||
|
|
||||||
#define SPI_SLAVE_HD_BUFFER_SIZE 64
|
|
||||||
@ -1081,6 +1081,29 @@ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uin
|
|||||||
//does not configure it in ESP32
|
//does not configure it in ESP32
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the spi communication command
|
||||||
|
*
|
||||||
|
* @param cmd_t Base command value
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
//This is not supported in esp32
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the dummy bits
|
||||||
|
*
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
//This is not supported in esp32
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
#undef SPI_LL_RST_MASK
|
#undef SPI_LL_RST_MASK
|
||||||
#undef SPI_LL_UNUSED_INT_MASK
|
#undef SPI_LL_UNUSED_INT_MASK
|
||||||
|
|
||||||
|
|||||||
@ -74,6 +74,21 @@ typedef enum {
|
|||||||
} spi_ll_trans_len_cond_t;
|
} spi_ll_trans_len_cond_t;
|
||||||
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
||||||
|
|
||||||
|
// SPI base command in esp32c2
|
||||||
|
typedef enum {
|
||||||
|
/* Slave HD Only */
|
||||||
|
SPI_LL_BASE_CMD_HD_WRBUF = 0x01,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDBUF = 0x02,
|
||||||
|
SPI_LL_BASE_CMD_HD_WRDMA = 0x03,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDDMA = 0x04,
|
||||||
|
SPI_LL_BASE_CMD_HD_SEG_END = 0x05,
|
||||||
|
SPI_LL_BASE_CMD_HD_EN_QPI = 0x06,
|
||||||
|
SPI_LL_BASE_CMD_HD_WR_END = 0x07,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT0 = 0x08,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT1 = 0x09,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT2 = 0x0A,
|
||||||
|
} spi_ll_base_command_t;
|
||||||
|
|
||||||
/*------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------
|
||||||
* Control
|
* Control
|
||||||
*----------------------------------------------------------------------------*/
|
*----------------------------------------------------------------------------*/
|
||||||
@ -1073,6 +1088,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
|
|||||||
return hw->slave1.last_addr;
|
return hw->slave1.last_addr;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the base spi command in esp32c2
|
||||||
|
*
|
||||||
|
* @param cmd_t Command value
|
||||||
|
*/
|
||||||
|
static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = 0x00;
|
||||||
|
switch (cmd_t)
|
||||||
|
{
|
||||||
|
case SPI_CMD_HD_WRBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WRDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_SEG_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_SEG_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_EN_QPI:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WR_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WR_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT0:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT0;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT1:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT1;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT2:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
HAL_ASSERT(cmd_base);
|
||||||
|
}
|
||||||
|
return cmd_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the spi communication command
|
||||||
|
*
|
||||||
|
* @param cmd_t Base command value
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t);
|
||||||
|
uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit
|
||||||
|
|
||||||
|
if (line_mode.data_lines == 2) {
|
||||||
|
if (line_mode.addr_lines == 2) {
|
||||||
|
cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit
|
||||||
|
}
|
||||||
|
} else if (line_mode.data_lines == 4) {
|
||||||
|
if (line_mode.addr_lines == 4) {
|
||||||
|
cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) {
|
||||||
|
cmd_mod = 0x00;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cmd_base | cmd_mod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the dummy bits
|
||||||
|
*
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
return 8;
|
||||||
|
}
|
||||||
|
|
||||||
#undef SPI_LL_RST_MASK
|
#undef SPI_LL_RST_MASK
|
||||||
#undef SPI_LL_UNUSED_INT_MASK
|
#undef SPI_LL_UNUSED_INT_MASK
|
||||||
|
|
||||||
|
|||||||
@ -74,6 +74,21 @@ typedef enum {
|
|||||||
} spi_ll_trans_len_cond_t;
|
} spi_ll_trans_len_cond_t;
|
||||||
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
||||||
|
|
||||||
|
// SPI base command in esp32c3
|
||||||
|
typedef enum {
|
||||||
|
/* Slave HD Only */
|
||||||
|
SPI_LL_BASE_CMD_HD_WRBUF = 0x01,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDBUF = 0x02,
|
||||||
|
SPI_LL_BASE_CMD_HD_WRDMA = 0x03,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDDMA = 0x04,
|
||||||
|
SPI_LL_BASE_CMD_HD_SEG_END = 0x05,
|
||||||
|
SPI_LL_BASE_CMD_HD_EN_QPI = 0x06,
|
||||||
|
SPI_LL_BASE_CMD_HD_WR_END = 0x07,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT0 = 0x08,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT1 = 0x09,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT2 = 0x0A,
|
||||||
|
} spi_ll_base_command_t;
|
||||||
|
|
||||||
/*------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------
|
||||||
* Control
|
* Control
|
||||||
*----------------------------------------------------------------------------*/
|
*----------------------------------------------------------------------------*/
|
||||||
@ -1076,6 +1091,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
|
|||||||
#undef SPI_LL_RST_MASK
|
#undef SPI_LL_RST_MASK
|
||||||
#undef SPI_LL_UNUSED_INT_MASK
|
#undef SPI_LL_UNUSED_INT_MASK
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the base spi command in esp32c3
|
||||||
|
*
|
||||||
|
* @param cmd_t Command value
|
||||||
|
*/
|
||||||
|
static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = 0x00;
|
||||||
|
switch (cmd_t)
|
||||||
|
{
|
||||||
|
case SPI_CMD_HD_WRBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WRDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_SEG_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_SEG_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_EN_QPI:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WR_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WR_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT0:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT0;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT1:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT1;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT2:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
HAL_ASSERT(cmd_base);
|
||||||
|
}
|
||||||
|
return cmd_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the spi communication command
|
||||||
|
*
|
||||||
|
* @param cmd_t Base command value
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t);
|
||||||
|
uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit
|
||||||
|
|
||||||
|
if (line_mode.data_lines == 2) {
|
||||||
|
if (line_mode.addr_lines == 2) {
|
||||||
|
cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit
|
||||||
|
}
|
||||||
|
} else if (line_mode.data_lines == 4) {
|
||||||
|
if (line_mode.addr_lines == 4) {
|
||||||
|
cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) {
|
||||||
|
cmd_mod = 0x00;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cmd_base | cmd_mod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the dummy bits
|
||||||
|
*
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
return 8;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -74,6 +74,21 @@ typedef enum {
|
|||||||
} spi_ll_trans_len_cond_t;
|
} spi_ll_trans_len_cond_t;
|
||||||
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
||||||
|
|
||||||
|
// SPI base command in esp32h2
|
||||||
|
typedef enum {
|
||||||
|
/* Slave HD Only */
|
||||||
|
SPI_LL_BASE_CMD_HD_WRBUF = 0x01,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDBUF = 0x02,
|
||||||
|
SPI_LL_BASE_CMD_HD_WRDMA = 0x03,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDDMA = 0x04,
|
||||||
|
SPI_LL_BASE_CMD_HD_SEG_END = 0x05,
|
||||||
|
SPI_LL_BASE_CMD_HD_EN_QPI = 0x06,
|
||||||
|
SPI_LL_BASE_CMD_HD_WR_END = 0x07,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT0 = 0x08,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT1 = 0x09,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT2 = 0x0A,
|
||||||
|
} spi_ll_base_command_t;
|
||||||
|
|
||||||
/*------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------
|
||||||
* Control
|
* Control
|
||||||
*----------------------------------------------------------------------------*/
|
*----------------------------------------------------------------------------*/
|
||||||
@ -1074,6 +1089,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
|
|||||||
#undef SPI_LL_RST_MASK
|
#undef SPI_LL_RST_MASK
|
||||||
#undef SPI_LL_UNUSED_INT_MASK
|
#undef SPI_LL_UNUSED_INT_MASK
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the base spi command in esp32h2
|
||||||
|
*
|
||||||
|
* @param cmd_t Command value
|
||||||
|
*/
|
||||||
|
static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = 0x00;
|
||||||
|
switch (cmd_t)
|
||||||
|
{
|
||||||
|
case SPI_CMD_HD_WRBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WRDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_SEG_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_SEG_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_EN_QPI:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WR_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WR_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT0:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT0;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT1:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT1;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT2:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
HAL_ASSERT(cmd_base);
|
||||||
|
}
|
||||||
|
return cmd_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the spi communication command
|
||||||
|
*
|
||||||
|
* @param cmd_t Base command value
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t);
|
||||||
|
uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit
|
||||||
|
|
||||||
|
if (line_mode.data_lines == 2) {
|
||||||
|
if (line_mode.addr_lines == 2) {
|
||||||
|
cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit
|
||||||
|
}
|
||||||
|
} else if (line_mode.data_lines == 4) {
|
||||||
|
if (line_mode.addr_lines == 4) {
|
||||||
|
cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) {
|
||||||
|
cmd_mod = 0x00;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cmd_base | cmd_mod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the dummy bits
|
||||||
|
*
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
return 4;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -84,6 +84,21 @@ typedef enum {
|
|||||||
} spi_ll_trans_len_cond_t;
|
} spi_ll_trans_len_cond_t;
|
||||||
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
||||||
|
|
||||||
|
// SPI base command in esp32s2
|
||||||
|
typedef enum {
|
||||||
|
/* Slave HD Only */
|
||||||
|
SPI_LL_BASE_CMD_HD_WRBUF = 0x01,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDBUF = 0x02,
|
||||||
|
SPI_LL_BASE_CMD_HD_WRDMA = 0x03,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDDMA = 0x04,
|
||||||
|
SPI_LL_BASE_CMD_HD_SEG_END = 0x05,
|
||||||
|
SPI_LL_BASE_CMD_HD_EN_QPI = 0x06,
|
||||||
|
SPI_LL_BASE_CMD_HD_WR_END = 0x07,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT0 = 0x08,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT1 = 0x09,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT2 = 0x0A,
|
||||||
|
} spi_ll_base_command_t;
|
||||||
|
|
||||||
/*------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------
|
||||||
* Control
|
* Control
|
||||||
*----------------------------------------------------------------------------*/
|
*----------------------------------------------------------------------------*/
|
||||||
@ -1278,6 +1293,104 @@ static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw)
|
|||||||
#undef SPI_LL_RST_MASK
|
#undef SPI_LL_RST_MASK
|
||||||
#undef SPI_LL_UNUSED_INT_MASK
|
#undef SPI_LL_UNUSED_INT_MASK
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the base spi command in esp32s2
|
||||||
|
*
|
||||||
|
* @param cmd_t Command value
|
||||||
|
*/
|
||||||
|
static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = 0x00;
|
||||||
|
switch (cmd_t)
|
||||||
|
{
|
||||||
|
case SPI_CMD_HD_WRBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WRDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_SEG_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_SEG_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_EN_QPI:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WR_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WR_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT0:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT0;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT1:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT1;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT2:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
HAL_ASSERT(cmd_base);
|
||||||
|
}
|
||||||
|
return cmd_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the spi communication command
|
||||||
|
*
|
||||||
|
* @param cmd_t Base command value
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t);
|
||||||
|
uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit
|
||||||
|
|
||||||
|
if (line_mode.data_lines == 2) {
|
||||||
|
if (line_mode.addr_lines == 2) {
|
||||||
|
cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit
|
||||||
|
}
|
||||||
|
} else if (line_mode.data_lines == 4) {
|
||||||
|
if (line_mode.addr_lines == 4) {
|
||||||
|
cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) {
|
||||||
|
cmd_mod = 0x00;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cmd_base | cmd_mod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the dummy bits
|
||||||
|
*
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
uint8_t dummy_bits = 0;
|
||||||
|
|
||||||
|
if (line_mode.data_lines == 2) {
|
||||||
|
dummy_bits = 4;
|
||||||
|
} else if (line_mode.data_lines == 4) {
|
||||||
|
dummy_bits = 4;
|
||||||
|
} else {
|
||||||
|
dummy_bits = 8;
|
||||||
|
}
|
||||||
|
|
||||||
|
HAL_ASSERT(dummy_bits);
|
||||||
|
return dummy_bits;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -76,6 +76,21 @@ typedef enum {
|
|||||||
} spi_ll_trans_len_cond_t;
|
} spi_ll_trans_len_cond_t;
|
||||||
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
FLAG_ATTR(spi_ll_trans_len_cond_t)
|
||||||
|
|
||||||
|
// SPI base command in esp32s3
|
||||||
|
typedef enum {
|
||||||
|
/* Slave HD Only */
|
||||||
|
SPI_LL_BASE_CMD_HD_WRBUF = 0x01,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDBUF = 0x02,
|
||||||
|
SPI_LL_BASE_CMD_HD_WRDMA = 0x03,
|
||||||
|
SPI_LL_BASE_CMD_HD_RDDMA = 0x04,
|
||||||
|
SPI_LL_BASE_CMD_HD_SEG_END = 0x05,
|
||||||
|
SPI_LL_BASE_CMD_HD_EN_QPI = 0x06,
|
||||||
|
SPI_LL_BASE_CMD_HD_WR_END = 0x07,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT0 = 0x08,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT1 = 0x09,
|
||||||
|
SPI_LL_BASE_CMD_HD_INT2 = 0x0A,
|
||||||
|
} spi_ll_base_command_t;
|
||||||
|
|
||||||
/*------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------
|
||||||
* Control
|
* Control
|
||||||
*----------------------------------------------------------------------------*/
|
*----------------------------------------------------------------------------*/
|
||||||
@ -1091,6 +1106,93 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
|
|||||||
#undef SPI_LL_RST_MASK
|
#undef SPI_LL_RST_MASK
|
||||||
#undef SPI_LL_UNUSED_INT_MASK
|
#undef SPI_LL_UNUSED_INT_MASK
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the base spi command in esp32s3
|
||||||
|
*
|
||||||
|
* @param cmd_t Command value
|
||||||
|
*/
|
||||||
|
static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = 0x00;
|
||||||
|
switch (cmd_t)
|
||||||
|
{
|
||||||
|
case SPI_CMD_HD_WRBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDBUF:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDBUF;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WRDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WRDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_RDDMA:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_RDDMA;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_SEG_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_SEG_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_EN_QPI:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_EN_QPI;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_WR_END:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_WR_END;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT0:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT0;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT1:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT1;
|
||||||
|
break;
|
||||||
|
case SPI_CMD_HD_INT2:
|
||||||
|
cmd_base = SPI_LL_BASE_CMD_HD_INT2;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
HAL_ASSERT(cmd_base);
|
||||||
|
}
|
||||||
|
return cmd_base;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the spi communication command
|
||||||
|
*
|
||||||
|
* @param cmd_t Base command value
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline uint16_t spi_ll_get_slave_hd_command(spi_command_t cmd_t, spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
uint8_t cmd_base = spi_ll_get_slave_hd_base_command(cmd_t);
|
||||||
|
uint8_t cmd_mod = 0x00; //CMD:1-bit, ADDR:1-bit, DATA:1-bit
|
||||||
|
|
||||||
|
if (line_mode.data_lines == 2) {
|
||||||
|
if (line_mode.addr_lines == 2) {
|
||||||
|
cmd_mod = 0x50; //CMD:1-bit, ADDR:2-bit, DATA:2-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x10; //CMD:1-bit, ADDR:1-bit, DATA:2-bit
|
||||||
|
}
|
||||||
|
} else if (line_mode.data_lines == 4) {
|
||||||
|
if (line_mode.addr_lines == 4) {
|
||||||
|
cmd_mod = 0xA0; //CMD:1-bit, ADDR:4-bit, DATA:4-bit
|
||||||
|
} else {
|
||||||
|
cmd_mod = 0x20; //CMD:1-bit, ADDR:1-bit, DATA:4-bit
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if (cmd_base == SPI_LL_BASE_CMD_HD_SEG_END || cmd_base == SPI_LL_BASE_CMD_HD_EN_QPI) {
|
||||||
|
cmd_mod = 0x00;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cmd_base | cmd_mod;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Get the dummy bits
|
||||||
|
*
|
||||||
|
* @param line_mode Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
|
||||||
|
*/
|
||||||
|
static inline int spi_ll_get_slave_hd_dummy_bits(spi_line_mode_t line_mode)
|
||||||
|
{
|
||||||
|
return 8;
|
||||||
|
}
|
||||||
|
|
||||||
#ifdef __cplusplus
|
#ifdef __cplusplus
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|||||||
@ -53,6 +53,22 @@ typedef struct {
|
|||||||
uint8_t data_lines; ///< The line width of data phase, e.g. 4-line-data-phase.
|
uint8_t data_lines; ///< The line width of data phase, e.g. 4-line-data-phase.
|
||||||
} spi_line_mode_t;
|
} spi_line_mode_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief SPI command.
|
||||||
|
*/
|
||||||
|
typedef enum {
|
||||||
|
/* Slave HD Only */
|
||||||
|
SPI_CMD_HD_WRBUF = BIT(0),
|
||||||
|
SPI_CMD_HD_RDBUF = BIT(1),
|
||||||
|
SPI_CMD_HD_WRDMA = BIT(2),
|
||||||
|
SPI_CMD_HD_RDDMA = BIT(3),
|
||||||
|
SPI_CMD_HD_SEG_END = BIT(4),
|
||||||
|
SPI_CMD_HD_EN_QPI = BIT(5),
|
||||||
|
SPI_CMD_HD_WR_END = BIT(6),
|
||||||
|
SPI_CMD_HD_INT0 = BIT(7),
|
||||||
|
SPI_CMD_HD_INT1 = BIT(8),
|
||||||
|
SPI_CMD_HD_INT2 = BIT(9),
|
||||||
|
} spi_command_t;
|
||||||
|
|
||||||
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
|
/** @cond */ //Doxy command to hide preprocessor definitions from docs */
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user