feat(esp_hw_support): support gdma register context sleep retention

components/esp_hw_support/CMakeLists.txt

@@ -70,6 +70,9 @@ if(NOT BOOTLOADER_BUILD)
 
     if(CONFIG_SOC_GDMA_SUPPORTED)
         list(APPEND srcs "dma/gdma.c")
+        if(CONFIG_SOC_PM_SUPPORT_TOP_PD)
+            list(APPEND srcs "dma/gdma_sleep_retention.c")
+        endif()
     endif()
 
     if(CONFIG_SOC_MULTI_USAGE_LDO_SUPPORTED)

components/esp_hw_support/dma/gdma.c

@@ -47,6 +47,10 @@
 #include "hal/cache_hal.h"
 #include "hal/cache_ll.h"
 
+#if CONFIG_PM_ENABLE && SOC_PM_SUPPORT_TOP_PD
+#include "esp_private/gdma_sleep_retention.h"
+#endif
+
 static const char *TAG = "gdma";
 
 #if !SOC_RCC_IS_INDEPENDENT
@@ -694,6 +698,9 @@ static void gdma_release_pair_handle(gdma_pair_t *pair)
 
     if (do_deinitialize) {
         free(pair);
+#if CONFIG_PM_ENABLE && SOC_PM_SUPPORT_TOP_PD
+        gdma_sleep_retention_deinit(group->group_id, pair_id);
+#endif
         ESP_LOGD(TAG, "del pair (%d,%d)", group->group_id, pair_id);
         gdma_release_group_handle(group);
     }
@@ -731,6 +738,9 @@ static gdma_pair_t *gdma_acquire_pair_handle(gdma_group_t *group, int pair_id)
         s_platform.group_ref_counts[group->group_id]++;
         portEXIT_CRITICAL(&s_platform.spinlock);
 
+#if CONFIG_PM_ENABLE && SOC_PM_SUPPORT_TOP_PD
+        gdma_sleep_retention_init(group->group_id, pair_id);
+#endif
         ESP_LOGD(TAG, "new pair (%d,%d) at %p", group->group_id, pair_id, pair);
     } else {
         free(pre_alloc_pair);

components/esp_hw_support/dma/gdma_sleep_retention.c

@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "sdkconfig.h"
+#include "soc/gdma_periph.h"
+#include "soc/soc_caps.h"
+
+#include "esp_err.h"
+#include "esp_check.h"
+#include "esp_log.h"
+#include "esp_private/sleep_retention.h"
+#include "esp_private/esp_regdma.h"
+
+#include "hal/gdma_ll.h"
+
+static const char *TAG = "gdma";
+
+esp_err_t gdma_sleep_retention_init(int group_id, int pair_id)
+{
+    sleep_retention_module_bitmap_t module = GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id);
+    esp_err_t err = sleep_retention_entries_create(gdma_chx_regs_retention[group_id][pair_id].link_list, gdma_chx_regs_retention[group_id][pair_id].link_num, REGDMA_LINK_PRI_7, module);
+    if (err == ESP_OK) {
+        ESP_LOGI(TAG, "GDMA pair (%d, %d) retention initialization", group_id, pair_id);
+    }
+
+    ESP_RETURN_ON_ERROR(err, TAG, "Failed to create sleep retention linked list for GDMA pair (%d, %d) retention", group_id, pair_id);
+    return err;
+}
+
+esp_err_t gdma_sleep_retention_deinit(int group_id, int pair_id)
+{
+    esp_err_t err = ESP_OK;
+    sleep_retention_entries_destroy(GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id));
+    return err;
+}

components/esp_hw_support/include/esp_private/gdma_sleep_retention.h

@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// DO NOT USE THESE APIS IN ANY APPLICATIONS
+// GDMA driver is not public for end users, but for ESP-IDF developers.
+
+#pragma once
+
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialize GDMA channel retention link for powerdown the TOP powerdomain during lightsleep
+ * @param  group_id Group id
+ * @param  pair_id  Pair id
+ * @return
+ *      - ESP_OK: Create DMA retention link successfully
+ *      - ESP_ERR_NO_MEM: Create DMA retention link failed because out of memory
+ */
+esp_err_t gdma_sleep_retention_init(int group_id, int pair_id);
+
+/**
+ * Destroy GDMA channel retention link
+ * @param  group_id Group id
+ * @param  pair_id  Pair id
+ * @return
+ *      - ESP_OK: GDMA channel retention link destrory successfully
+ *      - ESP_ERR_INVALID_STATE: GDMA channel retention link not create yet
+ */
+esp_err_t gdma_sleep_retention_deinit(int group_id, int pair_id);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/port/esp32c6/pmu_param.c

@@ -286,6 +286,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_modem2active_backup_en      = 0, \
     }, \
     .backup_clk = (                       \
+        BIT(PMU_ICG_FUNC_ENA_GDMA)      | \
         BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
         BIT(PMU_ICG_FUNC_ENA_TG0)       | \
         BIT(PMU_ICG_FUNC_ENA_TG1)       | \
@@ -335,6 +336,7 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_active2sleep_backup_en      = 0, \
     }, \
     .backup_clk = (                       \
+        BIT(PMU_ICG_FUNC_ENA_GDMA)      | \
         BIT(PMU_ICG_FUNC_ENA_REGDMA)    | \
         BIT(PMU_ICG_FUNC_ENA_TG0)       | \
         BIT(PMU_ICG_FUNC_ENA_TG1)       | \

components/esp_hw_support/port/esp32h2/pmu_param.c

@@ -290,7 +290,9 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_sleep2active_backup_en      = 0, \
         .hp_modem2active_backup_en      = 0, \
     }, \
-    .backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \
+    .backup_clk = (                             \
+        BIT(PMU_ICG_FUNC_ENA_GDMA)              \
+        | BIT(PMU_ICG_FUNC_ENA_REGDMA)          \
         | BIT(PMU_ICG_FUNC_ENA_TG0)             \
         | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
         | BIT(PMU_ICG_FUNC_ENA_MSPI)            \
@@ -337,7 +339,9 @@ const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_m
         .hp_modem2sleep_backup_en       = 0, \
         .hp_active2sleep_backup_en      = 0, \
     }, \
-    .backup_clk = (BIT(PMU_ICG_FUNC_ENA_REGDMA) \
+    .backup_clk = (                             \
+        BIT(PMU_ICG_FUNC_ENA_GDMA)              \
+        | BIT(PMU_ICG_FUNC_ENA_REGDMA)          \
         | BIT(PMU_ICG_FUNC_ENA_TG0)             \
         | BIT(PMU_ICG_FUNC_ENA_HPBUS)           \
         | BIT(PMU_ICG_FUNC_ENA_MSPI)            \

components/hal/esp32c6/include/hal/gdma_ll.h

@@ -13,11 +13,14 @@
 #include "soc/gdma_reg.h"
 #include "soc/soc_etm_source.h"
 #include "soc/pcr_struct.h"
+#include "soc/retention_periph_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id)
+
 #define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
 
 #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]

components/hal/esp32h2/include/hal/gdma_ll.h

@@ -13,11 +13,14 @@
 #include "soc/gdma_reg.h"
 #include "soc/soc_etm_source.h"
 #include "soc/pcr_struct.h"
+#include "soc/retention_periph_defs.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define GDMA_CH_RETENTION_GET_MODULE_ID(group_id, pair_id) (SLEEP_RETENTION_MODULE_GDMA_CH0 << (SOC_GDMA_PAIRS_PER_GROUP_MAX * group_id) << pair_id)
+
 #define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
 
 #define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]

components/soc/esp32c5/include/soc/retention_periph_defs.h

@@ -35,7 +35,9 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_IOMUX        = BIT(21),
     SLEEP_RETENTION_MODULE_SPIMEM       = BIT(22),
     SLEEP_RETENTION_MODULE_SYSTIMER     = BIT(23),
-
+    SLEEP_RETENTION_MODULE_GDMA_CH0     = BIT(24),
+    SLEEP_RETENTION_MODULE_GDMA_CH1     = BIT(25),
+    SLEEP_RETENTION_MODULE_GDMA_CH2     = BIT(26),
     SLEEP_RETENTION_MODULE_ALL          = (uint32_t)-1
 } periph_retention_module_bitmap_t;
 

components/soc/esp32c6/gdma_periph.c

@@ -5,6 +5,7 @@
  */
 
 #include "soc/gdma_periph.h"
+#include "soc/gdma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
     .groups = {
@@ -27,3 +28,74 @@ const gdma_signal_conn_t gdma_periph_signals = {
         }
     }
 };
+
+/* GDMA Channel (Group0, Pair0) Registers Context
+   Include: GDMA_MISC_CONF_REG /
+            GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
+            GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
+            GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
+*/
+#define G0P0_RETENTION_REGS_CNT  13
+#define G0P0_RETENTION_MAP_BASE  GDMA_IN_INT_ENA_CH0_REG
+static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
+static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
+                                                G0P0_RETENTION_REGS_CNT, 0, 0, \
+                                                g0p0_regs_map[0], g0p0_regs_map[1],   \
+                                                g0p0_regs_map[2], g0p0_regs_map[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+/* GDMA Channel (Group0, Pair1) Registers Context
+   Include: GDMA_MISC_CONF_REG /
+            GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
+            GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
+            GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
+*/
+#define G0P1_RETENTION_REGS_CNT  13
+#define G0P1_RETENTION_MAP_BASE  GDMA_IN_INT_ENA_CH1_REG
+static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
+static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
+                                                G0P1_RETENTION_REGS_CNT, 0, 0, \
+                                                g0p1_regs_map[0], g0p1_regs_map[1],   \
+                                                g0p1_regs_map[2], g0p1_regs_map[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+/* GDMA Channel (Group0, Pair2) Registers Context
+   Include: GDMA_MISC_CONF_REG /
+            GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
+            GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
+            GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
+*/
+#define G0P1_RETENTION_REGS_CNT_0  6
+#define G0P2_RETENTION_MAP_BASE_0  GDMA_IN_INT_ENA_CH2_REG
+#define G0P1_RETENTION_REGS_CNT_1  7
+#define G0P2_RETENTION_MAP_BASE_1  GDMA_IN_PRI_CH2_REG
+static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
+static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
+static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
+                                                G0P1_RETENTION_REGS_CNT_0, 0, 0, \
+                                                g0p2_regs_map0[0], g0p2_regs_map0[1],   \
+                                                g0p2_regs_map0[2], g0p2_regs_map0[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+    [1]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
+                                                G0P1_RETENTION_REGS_CNT_1, 0, 0, \
+                                                g0p2_regs_map1[0], g0p2_regs_map1[1],   \
+                                                g0p2_regs_map1[2], g0p2_regs_map1[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_PAIRS_PER_GROUP_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+    [0] = {
+        [0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
+        [1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
+        [2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)}
+    }
+};

components/soc/esp32c6/include/soc/retention_periph_defs.h

@@ -35,7 +35,9 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_IOMUX        = BIT(21),
     SLEEP_RETENTION_MODULE_SPIMEM       = BIT(22),
     SLEEP_RETENTION_MODULE_SYSTIMER     = BIT(23),
-
+    SLEEP_RETENTION_MODULE_GDMA_CH0     = BIT(24),
+    SLEEP_RETENTION_MODULE_GDMA_CH1     = BIT(25),
+    SLEEP_RETENTION_MODULE_GDMA_CH2     = BIT(26),
     SLEEP_RETENTION_MODULE_ALL          = (uint32_t)-1
 } periph_retention_module_bitmap_t;
 

components/soc/esp32h2/gdma_periph.c

@@ -5,6 +5,7 @@
  */
 
 #include "soc/gdma_periph.h"
+#include "soc/gdma_reg.h"
 
 const gdma_signal_conn_t gdma_periph_signals = {
     .groups = {
@@ -27,3 +28,74 @@ const gdma_signal_conn_t gdma_periph_signals = {
         }
     }
 };
+
+/* GDMA Channel (Group0, Pair0) Registers Context
+   Include: GDMA_MISC_CONF_REG /
+            GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
+            GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
+            GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
+*/
+#define G0P0_RETENTION_REGS_CNT  13
+#define G0P0_RETENTION_MAP_BASE  GDMA_IN_INT_ENA_CH0_REG
+static const uint32_t g0p0_regs_map[4] = {0x4C801001, 0x604C0060, 0, 0};
+static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P0_RETENTION_MAP_BASE, G0P0_RETENTION_MAP_BASE, \
+                                                G0P0_RETENTION_REGS_CNT, 0, 0, \
+                                                g0p0_regs_map[0], g0p0_regs_map[1],   \
+                                                g0p0_regs_map[2], g0p0_regs_map[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+/* GDMA Channel (Group0, Pair1) Registers Context
+   Include: GDMA_MISC_CONF_REG /
+            GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
+            GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
+            GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
+*/
+#define G0P1_RETENTION_REGS_CNT  13
+#define G0P1_RETENTION_MAP_BASE  GDMA_IN_INT_ENA_CH1_REG
+static const uint32_t g0p1_regs_map[4] = {0x81001, 0, 0xC00604C0, 0x604};
+static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P1_RETENTION_MAP_BASE, G0P1_RETENTION_MAP_BASE, \
+                                                G0P1_RETENTION_REGS_CNT, 0, 0, \
+                                                g0p1_regs_map[0], g0p1_regs_map[1],   \
+                                                g0p1_regs_map[2], g0p1_regs_map[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+/* GDMA Channel (Group0, Pair2) Registers Context
+   Include: GDMA_MISC_CONF_REG /
+            GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG / GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
+            GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
+            GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
+*/
+#define G0P1_RETENTION_REGS_CNT_0  6
+#define G0P2_RETENTION_MAP_BASE_0  GDMA_IN_INT_ENA_CH2_REG
+#define G0P1_RETENTION_REGS_CNT_1  7
+#define G0P2_RETENTION_MAP_BASE_1  GDMA_IN_PRI_CH2_REG
+static const uint32_t g0p2_regs_map0[4] = {0x9001, 0, 0, 0x4C0000};
+static const uint32_t g0p2_regs_map1[4] = {0x3026003, 0, 0, 0};
+static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
+    [0]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
+                                                G0P1_RETENTION_REGS_CNT_0, 0, 0, \
+                                                g0p2_regs_map0[0], g0p2_regs_map0[1],   \
+                                                g0p2_regs_map0[2], g0p2_regs_map0[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+    [1]  = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GDMA_LINK(0x00), \
+                                                G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
+                                                G0P1_RETENTION_REGS_CNT_1, 0, 0, \
+                                                g0p2_regs_map1[0], g0p2_regs_map1[1],   \
+                                                g0p2_regs_map1[2], g0p2_regs_map1[3]),  \
+                                                .owner = ENTRY(0) | ENTRY(2) },
+};
+
+const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_PAIRS_PER_GROUP_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
+    [0] = {
+        [0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
+        [1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
+        [2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)}
+    }
+};

components/soc/esp32h2/include/soc/retention_periph_defs.h

@@ -33,7 +33,9 @@ typedef enum periph_retention_module_bitmap {
     SLEEP_RETENTION_MODULE_IOMUX        = BIT(21),
     SLEEP_RETENTION_MODULE_SPIMEM       = BIT(22),
     SLEEP_RETENTION_MODULE_SYSTIMER     = BIT(23),
-
+    SLEEP_RETENTION_MODULE_GDMA_CH0     = BIT(24),
+    SLEEP_RETENTION_MODULE_GDMA_CH1     = BIT(25),
+    SLEEP_RETENTION_MODULE_GDMA_CH2     = BIT(26),
     SLEEP_RETENTION_MODULE_ALL          = (uint32_t)-1
 } periph_retention_module_bitmap_t;
 

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1335,10 +1335,6 @@ config SOC_PM_SUPPORT_VDDSDIO_PD
     bool
     default y
 
-config SOC_PM_SUPPORT_TOP_PD
-    bool
-    default y
-
 config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -560,7 +560,7 @@
 #define SOC_PM_SUPPORT_RC32K_PD         (1)
 #define SOC_PM_SUPPORT_RC_FAST_PD       (1)
 #define SOC_PM_SUPPORT_VDDSDIO_PD       (1)
-#define SOC_PM_SUPPORT_TOP_PD           (1)
+// #define SOC_PM_SUPPORT_TOP_PD           (1) // TODO: IDF-7531
 
 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY   (1) /*!<Supports CRC only the stub code in RTC memory */
 

components/soc/include/soc/gdma_periph.h

@@ -9,6 +9,10 @@
 #include "soc/soc_caps.h"
 #include "soc/periph_defs.h"
 
+#if SOC_PM_SUPPORT_TOP_PD
+#include "soc/regdma.h"
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -26,6 +30,15 @@ typedef struct {
 
 extern const gdma_signal_conn_t gdma_periph_signals;
 
+#if SOC_PM_SUPPORT_TOP_PD
+typedef struct {
+    const regdma_entries_config_t *link_list;
+    uint32_t link_num;
+} gdma_chx_reg_ctx_link_t;
+
+extern const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_PAIRS_PER_GROUP_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX];
+#endif
+
 #endif
 
 #ifdef __cplusplus

components/soc/include/soc/regdma.h

@@ -9,6 +9,7 @@
 #include <stddef.h>
 #include <stdint.h>
 #include "esp_assert.h"
+#include "esp_bit_defs.h"
 #include "soc/soc_caps.h"
 
 #ifdef __cplusplus
@@ -42,6 +43,7 @@ extern "C" {
 #define REGDMA_BLE_MAC_LINK(_pri)           ((0x15 << 8) | _pri)
 #define REGDMA_MODEM_BT_BB_LINK(_pri)       ((0x16 << 8) | _pri)
 #define REGDMA_MODEM_IEEE802154_LINK(_pri)  ((0x17 << 8) | _pri)
+#define REGDMA_GDMA_LINK(_pri)              ((0x18 << 8) | _pri)
 #define REGDMA_MODEM_FE_LINK(_pri)          ((0xFF << 8) | _pri)
 
 typedef enum {