alex/esp-idf
alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2024-10-05 20:47:46 -04:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

Merge branch 'bugfix/fix_memory_miss_bug_esp32c3_esp32s3' into 'master'

Browse Source 
ESP32C3/ESP32S3: Fix cpu crash bug  when wakeup from lightsleep for memory data miss

Closes IDF-162 and IDF-4923

See merge request espressif/esp-idf!17823
This commit is contained in:
Michael (XIAO Xufeng) 2022-05-18 12:05:08 +08:00
commit 0adb814af3
4 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
components/esp_hw_support/port/esp32c3/rtc_sleep.c
View File

@ -161,6 +161,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
} }
/* mem force pu */
SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
if (!cfg.int_8m_pd_en) { if (!cfg.int_8m_pd_en) {
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);

6
components/esp_hw_support/port/esp32s3/rtc_sleep.c
View File

@ -29,7 +29,6 @@
*/ */
void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
{ {
#if !CONFIG_IDF_ENV_FPGA
REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
@ -43,7 +42,6 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
#endif
if (cfg.sram_fpu) { if (cfg.sram_fpu) {
REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP); REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
} else { } else {
@ -170,8 +168,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
} }
/* mem pd */ /* mem force pu */
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU);
if (!cfg.int_8m_pd_en) { if (!cfg.int_8m_pd_en) {
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);

5
components/soc/esp32c3/include/soc/rtc.h
View File

@ -58,9 +58,8 @@ extern "C" {
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/ */
#define RTC_CNTL_DBIAS_SLP 0 //sleep dig_dbias & rtc_dbias #define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage #define RTC_CNTL_DBIAS_0V90 13 //digital voltage
#define RTC_CNTL_DBIAS_0V95 16 #define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18 #define RTC_CNTL_DBIAS_1V00 18
@ -105,7 +104,7 @@ extern "C" {
/* /*
set sleep_init default param set sleep_init default param
*/ */
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 3 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0

3
components/soc/esp32s3/include/soc/rtc.h
View File

@ -59,9 +59,8 @@ extern "C" {
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
* Valid if RTC_CNTL_DBG_ATTEN is 0.
*/ */
#define RTC_CNTL_DBIAS_SLP 0 ///< sleep dig_dbias & rtc_dbias #define RTC_CNTL_DBIAS_SLP 5 ///< sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 ///< digital voltage #define RTC_CNTL_DBIAS_0V90 13 ///< digital voltage
#define RTC_CNTL_DBIAS_0V95 16 #define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18 #define RTC_CNTL_DBIAS_1V00 18