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Merge branch 'bugfix/fix_btld_app_overlap_c2_v5.0' into 'release/v5.0'

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ld: fixed bootloader and app potential overlap issue (v5.0)

See merge request espressif/esp-idf!22569
This commit is contained in:
morris 2023-03-02 15:26:02 +08:00
commit 0a5ed6ff9c
4 changed files with 18 additions and 2 deletions
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8
components/bootloader/subproject/main/ld/esp32c2/bootloader.ld
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@ -42,6 +42,14 @@ MEMORY
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* The app may use RAM for static allocations up to the start of iram_loader_seg.
* If you have changed something above and this assert fails:
* 1. Check what the new value of bootloader_iram_loader_seg start is.
* 2. Update the value in this assert.
* 3. Update (SRAM_DRAM_END + I_D_SRAM_OFFSET) in components/esp_system/ld/esp32c2/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x403aeb70, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(call_start_cpu0);

8
components/bootloader/subproject/main/ld/esp32c3/bootloader.ld
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@ -42,6 +42,14 @@ MEMORY
dram_seg (RW) : org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
}
/* The app may use RAM for static allocations up to the start of iram_loader_seg.
* If you have changed something above and this assert fails:
* 1. Check what the new value of bootloader_iram_loader_seg start is.
* 2. Update the value in this assert.
* 3. Update (SRAM_DRAM_END + I_D_SRAM_OFFSET) in components/esp_system/ld/esp32c3/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x403ce710, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(call_start_cpu0);

2
components/esp_system/ld/esp32c2/memory.ld.in
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@ -13,7 +13,7 @@
#define SRAM_DRAM_START 0x3FCA0000
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C2 */
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_END 0x403B0000 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_DRAM_END 0x403AEB70 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_ORG (SRAM_DRAM_START)

2
components/esp_system/ld/esp32c3/memory.ld.in
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@ -31,7 +31,7 @@
#define SRAM_DRAM_START 0x3FC7C000
#define ICACHE_SIZE 0x4000 /* ICache size is fixed to 16KB on ESP32-C3 */
#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START)
#define SRAM_DRAM_END 0x403CF600 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_DRAM_END 0x403CE710 - I_D_SRAM_OFFSET /* 2nd stage bootloader iram_loader_seg start address */
#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE)
#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE)