diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index 56d0def619..50841152d2 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -129,15 +129,9 @@ menu "ESP System Settings" for the data part (above the splitting address). The memory protection is effective on all access through the IRAM0 and DRAM0 buses. - config ESP_SYSTEM_MEMPROT_DEPCHECK - bool - default y if IDF_TARGET_ESP32S2 - default y if IDF_TARGET_ESP32C3 - default y if IDF_TARGET_ESP32S3 - config ESP_SYSTEM_MEMPROT_FEATURE bool "Enable memory protection" - depends on ESP_SYSTEM_MEMPROT_DEPCHECK + depends on SOC_MEMPROT_SUPPORTED default "y" help If enabled, the permission control module watches all the memory access and fires the panic handler @@ -155,20 +149,6 @@ menu "ESP System Settings" Once locked, memory protection settings cannot be changed anymore. The lock is reset only on the chip startup. - config ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE - # Hidden option for linker script usage - int - depends on ESP_SYSTEM_MEMPROT_DEPCHECK - default 16 - - config ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE - # Hidden option for linker script usage - int - depends on ESP_SYSTEM_MEMPROT_DEPCHECK - default 4 if IDF_TARGET_ESP32S2 - default 256 if IDF_TARGET_ESP32S3 - default 512 - endmenu # Memory protection config ESP_SYSTEM_EVENT_QUEUE_SIZE diff --git a/components/esp_system/ld/ld.common b/components/esp_system/ld/ld.common index e43cf19f85..26607f9263 100644 --- a/components/esp_system/ld/ld.common +++ b/components/esp_system/ld/ld.common @@ -10,15 +10,15 @@ _esp_flash_mmap_prefetch_pad_size = 16; /* CPU instruction prefetch padding size for memory protection scenario */ -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE -_esp_memprot_prefetch_pad_size = CONFIG_ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE; +#ifdef CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE +_esp_memprot_prefetch_pad_size = CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE; #else _esp_memprot_prefetch_pad_size = 0; #endif /* Memory alignment size for PMS */ -#ifdef CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE -_esp_memprot_align_size = CONFIG_ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE; +#ifdef CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE +_esp_memprot_align_size = CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE; #else _esp_memprot_align_size = 0; #endif diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 6a22ee0708..8835561b61 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -103,6 +103,10 @@ config SOC_SECURE_BOOT_SUPPORTED bool default y +config SOC_MEMPROT_SUPPORTED + bool + default y + config SOC_AES_SUPPORT_DMA bool default y @@ -675,6 +679,14 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128 bool default y +config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE + int + default 16 + +config SOC_MEMPROT_MEM_ALIGN_SIZE + int + default 512 + config SOC_UART_NUM int default 2 diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index a9bd7a0ee1..c92c664a50 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -53,6 +53,7 @@ * bootloader "security" configuration and accordingly prevent its usage for ECO2 and * earlier revisions */ #define SOC_SECURE_BOOT_SUPPORTED 1 +#define SOC_MEMPROT_SUPPORTED 1 /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) @@ -317,6 +318,10 @@ #define SOC_FLASH_ENCRYPTION_XTS_AES 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 +/*-------------------------- MEMPROT CAPS ------------------------------------*/ +#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define SOC_MEMPROT_MEM_ALIGN_SIZE 512 + /*-------------------------- UART CAPS ---------------------------------------*/ // ESP32-C3 has 2 UARTs #define SOC_UART_NUM (2) diff --git a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in index d903cd9218..ad103cccde 100644 --- a/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s2/include/soc/Kconfig.soc_caps.in @@ -127,6 +127,10 @@ config SOC_SECURE_BOOT_SUPPORTED bool default y +config SOC_MEMPROT_SUPPORTED + bool + default y + config SOC_ADC_RTC_CTRL_SUPPORTED bool default y @@ -775,6 +779,14 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_256 bool default y +config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE + int + default 16 + +config SOC_MEMPROT_MEM_ALIGN_SIZE + int + default 4 + config SOC_AES_CRYPTO_DMA bool default y diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 6cf7386743..24ed94ac4a 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -70,6 +70,7 @@ #define SOC_DIG_SIGN_SUPPORTED 1 #define SOC_FLASH_ENC_SUPPORTED 1 #define SOC_SECURE_BOOT_SUPPORTED 1 +#define SOC_MEMPROT_SUPPORTED 1 /*-------------------------- ADC CAPS ----------------------------------------*/ @@ -354,6 +355,10 @@ #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 +/*-------------------------- MEMPROT CAPS ------------------------------------*/ +#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define SOC_MEMPROT_MEM_ALIGN_SIZE 4 + /* Has "crypto DMA", which is shared with SHA */ #define SOC_AES_CRYPTO_DMA (1) diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index 5d66095824..ff51e5f55c 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -183,6 +183,10 @@ config SOC_SECURE_BOOT_SUPPORTED bool default y +config SOC_MEMPROT_SUPPORTED + bool + default y + config SOC_APPCPU_HAS_CLOCK_GATING_BUG bool default y @@ -907,6 +911,14 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_256 bool default y +config SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE + int + default 16 + +config SOC_MEMPROT_MEM_ALIGN_SIZE + int + default 256 + config SOC_PHY_DIG_REGS_MEM_SIZE int default 21 diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index 3f21cfeae8..c4b63cf5ef 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -60,6 +60,7 @@ #define SOC_DIG_SIGN_SUPPORTED 1 #define SOC_FLASH_ENC_SUPPORTED 1 #define SOC_SECURE_BOOT_SUPPORTED 1 +#define SOC_MEMPROT_SUPPORTED 1 /*-------------------------- SOC CAPS ----------------------------------------*/ @@ -390,6 +391,10 @@ #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 #define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 +/*-------------------------- MEMPROT CAPS ------------------------------------*/ +#define SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE 16 +#define SOC_MEMPROT_MEM_ALIGN_SIZE 256 + /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) #define SOC_MAC_BB_PD_MEM_SIZE (192*4)