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Merge branch 'bugfix/boot_flash_build_v5.1' into 'release/v5.1'

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bugfix(spi_flash): Fix build error when octal flash is enabled (5.1)

See merge request espressif/esp-idf!28078
This commit is contained in:
morris 2023-12-25 10:02:08 +08:00
commit 08545547d8
2 changed files with 50 additions and 3 deletions
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9
components/bootloader_support/bootloader_flash/include/bootloader_flash.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -54,6 +54,13 @@ esp_err_t bootloader_flash_reset_chip(void);
*/
bool bootloader_flash_is_octal_mode_enabled(void);
/**
* @brief Get the spi flash working mode.
*
* @return The mode of flash working mode, see `esp_rom_spiflash_read_mode_t`
*/
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void);
#ifdef __cplusplus
}
#endif

44
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
View File

@ -124,6 +124,9 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
#include "hal/mmu_hal.h"
#include "hal/mmu_ll.h"
#include "hal/cache_hal.h"
#if CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/opi_flash.h"
#endif
static const char *TAG = "bootloader_flash";
#if CONFIG_IDF_TARGET_ESP32
@ -431,9 +434,9 @@ void bootloader_flash_32bits_address_map_enable(esp_rom_spiflash_read_mode_t fla
assert(false);
break;
}
cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
cache_hal_disable(CACHE_TYPE_ALL);
esp_rom_opiflash_cache_mode_config(flash_mode, &cache_rd);
cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL);
cache_hal_enable(CACHE_TYPE_ALL);
}
#endif
@ -783,3 +786,40 @@ bool IRAM_ATTR bootloader_flash_is_octal_mode_enabled(void)
return false;
#endif
}
esp_rom_spiflash_read_mode_t bootloader_flash_get_spi_mode(void)
{
esp_rom_spiflash_read_mode_t spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
#if CONFIG_IDF_TARGET_ESP32
uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
if (spi_ctrl & SPI_FREAD_QIO) {
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
} else if (spi_ctrl & SPI_FREAD_QUAD) {
spi_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
} else if (spi_ctrl & SPI_FREAD_DIO) {
spi_mode = ESP_ROM_SPIFLASH_DIO_MODE;
} else if (spi_ctrl & SPI_FREAD_DUAL) {
spi_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
} else if (spi_ctrl & SPI_FASTRD_MODE) {
spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
} else {
spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
}
#else
uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
if (spi_ctrl & SPI_MEM_FREAD_QIO) {
spi_mode = ESP_ROM_SPIFLASH_QIO_MODE;
} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
spi_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
spi_mode = ESP_ROM_SPIFLASH_DIO_MODE;
} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
spi_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
spi_mode = ESP_ROM_SPIFLASH_FASTRD_MODE;
} else {
spi_mode = ESP_ROM_SPIFLASH_SLOWRD_MODE;
}
#endif
return spi_mode;
}