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Merge branch 'feature/c61_remove_lp_core' into 'master'

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feat(ulp): remove ulp related C61 code

Closes IDF-9331 and IDF-9330

See merge request espressif/esp-idf!33116
This commit is contained in:
Marius Vikhammer 2024-08-28 09:51:48 +08:00
commit 079df0282a
5 changed files with 0 additions and 19 deletions
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1
components/esp_hw_support/rtc_module.c
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@ -20,7 +20,6 @@
#include "esp_private/rtc_ctrl.h" #include "esp_private/rtc_ctrl.h"
#include "esp_attr.h" #include "esp_attr.h"
//TODO: [ESP32C61] IDF-9331, c61 don't have lp-core, check
#ifndef NDEBUG #ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds // Enable built-in checks in queue.h in debug builds

5
components/esp_system/ld/esp32c61/memory.ld.in
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@ -63,12 +63,7 @@ MEMORY
/** /**
* lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667 * lp ram memory (RWX). Persists over deep sleep. // TODO: IDF-5667
*/ */
#if CONFIG_ULP_COPROC_ENABLED
lp_ram_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
len = 0x4000 - CONFIG_ULP_COPROC_RESERVE_MEM - RESERVE_RTC_MEM
#else
lp_ram_seg(RW) : org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM lp_ram_seg(RW) : org = 0x50000000, len = 0x4000 - RESERVE_RTC_MEM
#endif // CONFIG_ULP_COPROC_ENABLED
/* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value. /* We reduced the size of lp_ram_seg by RESERVE_RTC_MEM value.
It reserves the amount of LP memory that we use for this memory segment. It reserves the amount of LP memory that we use for this memory segment.

3
components/soc/esp32c61/include/soc/soc_caps.h
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@ -30,7 +30,6 @@
// \#define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32C61] IDF-9322 // \#define SOC_TEMP_SENSOR_SUPPORTED 1 //TODO: [ESP32C61] IDF-9322
// \#define SOC_WIFI_SUPPORTED 1 // \#define SOC_WIFI_SUPPORTED 1
#define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1
// \#define SOC_ULP_SUPPORTED 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1 #define SOC_EFUSE_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1 #define SOC_RTC_FAST_MEM_SUPPORTED 1
@ -62,10 +61,8 @@
// \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336 // \#define SOC_TWAI_SUPPORTED 0 //TODO: [ESP32C61] IDF-9336
// \#define SOC_ETM_SUPPORTED 0 // \#define SOC_ETM_SUPPORTED 0
// \#define SOC_LP_CORE_SUPPORTED 0 //TODO: [ESP32C61] IDF-9331
// \#define SOC_SDIO_SLAVE_SUPPORTED 0 // \#define SOC_SDIO_SLAVE_SUPPORTED 0
// \#define SOC_PAU_SUPPORTED 0 // \#define SOC_PAU_SUPPORTED 0
// \#define SOC_LP_I2C_SUPPORTED 0 //TODO: [ESP32C61] IDF-9330, IDF-9337
// \#define SOC_PM_SUPPORTED 1 // \#define SOC_PM_SUPPORTED 1
#define SOC_ECDSA_SUPPORTED 1 #define SOC_ECDSA_SUPPORTED 1
#define SOC_SPIRAM_SUPPORTED 1 #define SOC_SPIRAM_SUPPORTED 1

5
components/soc/esp32c61/include/soc/soc_etm_source.h
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@ -86,9 +86,6 @@
#define I2S1_EVT_TX_DONE 78 #define I2S1_EVT_TX_DONE 78
#define I2S1_EVT_X_WORDS_RECEIVED 79 #define I2S1_EVT_X_WORDS_RECEIVED 79
#define I2S1_EVT_X_WORDS_SENT 80 #define I2S1_EVT_X_WORDS_SENT 80
#define ULP_EVT_ERR_INTR 81
#define ULP_EVT_HALT 82
#define ULP_EVT_START_INTR 83
#define RTC_EVT_TICK 84 #define RTC_EVT_TICK 84
#define RTC_EVT_OVF 85 #define RTC_EVT_OVF 85
#define RTC_EVT_CMP 86 #define RTC_EVT_CMP 86
@ -229,8 +226,6 @@
#define I2S1_TASK_START_TX 116 #define I2S1_TASK_START_TX 116
#define I2S1_TASK_STOP_RX 117 #define I2S1_TASK_STOP_RX 117
#define I2S1_TASK_STOP_TX 118 #define I2S1_TASK_STOP_TX 118
#define ULP_TASK_WAKEUP_CPU 119
#define ULP_TASK_INT_CPU 120
#define RTC_TASK_START 121 #define RTC_TASK_START 121
#define RTC_TASK_STOP 122 #define RTC_TASK_STOP 122
#define RTC_TASK_CLR 123 #define RTC_TASK_CLR 123

5
docs/docs_not_updated/esp32c61.txt
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@ -136,12 +136,8 @@ api-reference/system/sleep_modes.rst
api-reference/system/mm_sync.rst api-reference/system/mm_sync.rst
api-reference/system/ota.rst api-reference/system/ota.rst
api-reference/system/app_trace.rst api-reference/system/app_trace.rst
api-reference/system/ulp_macros.rst
api-reference/system/ulp-lp-core.rst
api-reference/system/ulp.rst
api-reference/system/efuse.rst api-reference/system/efuse.rst
api-reference/system/chip_revision.rst api-reference/system/chip_revision.rst
api-reference/system/ulp_instruction_set.rst
api-reference/system/async_memcpy.rst api-reference/system/async_memcpy.rst
api-reference/system/random.rst api-reference/system/random.rst
api-reference/system/esp_timer.rst api-reference/system/esp_timer.rst
@ -183,7 +179,6 @@ api-reference/system/inc/power_management_esp32c2.rst
api-reference/system/inc/show-efuse-table_ESP32-S2.rst api-reference/system/inc/show-efuse-table_ESP32-S2.rst
api-reference/system/mm.rst api-reference/system/mm.rst
api-reference/system/esp_https_ota.rst api-reference/system/esp_https_ota.rst
api-reference/system/ulp-risc-v.rst
api-reference/system/index.rst api-reference/system/index.rst
api-reference/bluetooth/esp_spp.rst api-reference/bluetooth/esp_spp.rst
api-reference/bluetooth/esp_l2cap_bt.rst api-reference/bluetooth/esp_l2cap_bt.rst