diff --git a/components/soc/esp32/include/soc/mmu.h b/components/soc/esp32/include/soc/mmu.h new file mode 100644 index 0000000000..bde6995516 --- /dev/null +++ b/components/soc/esp32/include/soc/mmu.h @@ -0,0 +1,42 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "soc/dport_reg.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 4 +#define SOC_MMU_PAGES_PER_REGION 64 +#define SOC_MMU_IROM0_PAGES_START 64 +#define SOC_MMU_IROM0_PAGES_END 256 +#define SOC_MMU_DROM0_PAGES_START 0 +#define SOC_MMU_DROM0_PAGES_END 64 +#define SOC_MMU_INVALID_ENTRY_VAL DPORT_FLASH_MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK +#define SOC_MMU_PAGE_IN_FLASH(page) (page) +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) 0x3FF10000) +#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START) +#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/include/soc/mmu.h b/components/soc/esp32c3/include/soc/mmu.h new file mode 100644 index 0000000000..d8db3d5c12 --- /dev/null +++ b/components/soc/esp32c3/include/soc/mmu.h @@ -0,0 +1,42 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "soc/cache_memory.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 1 +#define SOC_MMU_PAGES_PER_REGION 128 +#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK +#define SOC_MMU_PAGE_IN_FLASH(page) (page) //Always in Flash +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define SOC_MMU_VADDR1_START_ADDR SOC_IRAM_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START +#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 544479edd0..92a40af326 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -262,22 +262,6 @@ // Start (highest address) of ROM boot stack, only relevant during early boot #define SOC_ROM_STACK_START 0x3fcebf10 -/* Defined for flash mmap */ -#define REGIONS_COUNT 1 -#define PAGES_PER_REGION 128 -#define IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) -#define IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) -#define DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) -#define DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) -#define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL -#define MMU_ADDR_MASK MMU_ADDRESS_MASK -#define PAGE_IN_FLASH(page) (page) //Always in Flash -#define DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE -#define VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW -#define PRO_IRAM0_FIRST_USABLE_PAGE IROM0_PAGES_START -#define VADDR0_START_ADDR (SOC_DROM_LOW + (DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) -#define VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW - //interrupt cpu using table, Please see the core-isa.h /************************************************************************************************************* * Intr num Level Type PRO CPU usage APP CPU uasge diff --git a/components/soc/esp32s2/include/soc/mmu.h b/components/soc/esp32s2/include/soc/mmu.h new file mode 100644 index 0000000000..44f716f217 --- /dev/null +++ b/components/soc/esp32s2/include/soc/mmu.h @@ -0,0 +1,42 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "soc/cache_memory.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 6 +#define SOC_MMU_PAGES_PER_REGION 64 +#define SOC_MMU_IROM0_PAGES_START (PRO_CACHE_IBUS0_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_IROM0_PAGES_END (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK +#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define SOC_MMU_VADDR1_START_ADDR SOC_IROM_MASK_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE ((SOC_MMU_VADDR1_FIRST_USABLE_ADDR - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START) +#define SOC_MMU_VADDR0_START_ADDR SOC_DROM_LOW +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32s3/include/soc/mmu.h b/components/soc/esp32s3/include/soc/mmu.h new file mode 100644 index 0000000000..a38cb9eb42 --- /dev/null +++ b/components/soc/esp32s3/include/soc/mmu.h @@ -0,0 +1,42 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include "soc/cache_memory.h" +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Defined for flash mmap */ +#define SOC_MMU_REGIONS_COUNT 2 +#define SOC_MMU_PAGES_PER_REGION 256 +#define SOC_MMU_IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) +#define SOC_MMU_DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) +#define SOC_MMU_INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL +#define SOC_MMU_ADDR_MASK MMU_ADDRESS_MASK +#define SOC_MMU_PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) +#define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE +#define SOC_MMU_VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW +#define SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE SOC_MMU_IROM0_PAGES_START +#define SOC_MMU_VADDR0_START_ADDR (SOC_DROM_LOW + (SOC_MMU_DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) +#define SOC_MMU_VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW + +#ifdef __cplusplus +} +#endif diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index 1ba148f0ac..7b221dd064 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -35,22 +35,26 @@ #include "esp32/rom/cache.h" #include "esp32/rom/spi_flash.h" #include "esp32/spiram.h" +#include "soc/mmu.h" #elif CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/rom/cache.h" #include "esp32s2/rom/spi_flash.h" #include "esp32s2/spiram.h" #include "soc/extmem_reg.h" #include "soc/cache_memory.h" +#include "soc/mmu.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/spi_flash.h" #include "esp32s3/rom/cache.h" #include "esp32s3/spiram.h" #include "soc/extmem_reg.h" #include "soc/cache_memory.h" +#include "soc/mmu.h" #elif CONFIG_IDF_TARGET_ESP32C3 #include "esp32c3/rom/cache.h" #include "esp32c3/rom/spi_flash.h" #include "soc/cache_memory.h" +#include "soc/mmu.h" #endif #ifndef NDEBUG @@ -59,53 +63,9 @@ #endif #include "sys/queue.h" -#ifdef CONFIG_IDF_TARGET_ESP32 -#define PAGES_PER_REGION 64 -#define REGIONS_COUNT 4 -#define IROM0_PAGES_START 64 -#define IROM0_PAGES_END 256 -#define DROM0_PAGES_START 0 -#define DROM0_PAGES_END 64 -#define PAGE_IN_FLASH(page) (page) -#define INVALID_ENTRY_VAL DPORT_FLASH_MMU_TABLE_INVALID_VAL -#define MMU_ADDR_MASK DPORT_MMU_ADDRESS_MASK -#define VADDR1_START_ADDR 0x40000000 -#define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START) -#define VADDR0_START_ADDR SOC_DROM_LOW -#elif CONFIG_IDF_TARGET_ESP32S2 -#define PAGES_PER_REGION 64 -#define REGIONS_COUNT 6 -#define IROM0_PAGES_START (PRO_CACHE_IBUS0_MMU_START / sizeof(uint32_t)) -#define IROM0_PAGES_END (PRO_CACHE_IBUS1_MMU_END / sizeof(uint32_t)) -#define DROM0_PAGES_START (PRO_CACHE_IBUS2_MMU_START / sizeof(uint32_t)) -#define DROM0_PAGES_END (PRO_CACHE_IBUS2_MMU_END / sizeof(uint32_t)) -#define DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE -#define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL -#define MMU_ADDR_MASK MMU_ADDRESS_MASK -#define PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) -#define VADDR1_START_ADDR 0x40000000 -#define PRO_IRAM0_FIRST_USABLE_PAGE ((VADDR1_FIRST_USABLE_ADDR - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START) -#define VADDR0_START_ADDR SOC_DROM_LOW -#elif CONFIG_IDF_TARGET_ESP32S3 -#define REGIONS_COUNT 2 -#define PAGES_PER_REGION 256 -#define IROM0_PAGES_START (CACHE_IROM_MMU_START / sizeof(uint32_t)) -#define IROM0_PAGES_END (CACHE_IROM_MMU_END / sizeof(uint32_t)) -#define DROM0_PAGES_START (CACHE_DROM_MMU_START / sizeof(uint32_t)) -#define DROM0_PAGES_END (CACHE_DROM_MMU_END / sizeof(uint32_t)) -#define DPORT_PRO_FLASH_MMU_TABLE FLASH_MMU_TABLE -#define INVALID_ENTRY_VAL MMU_TABLE_INVALID_VAL -#define MMU_ADDR_MASK MMU_ADDRESS_MASK -#define PAGE_IN_FLASH(page) ((page) | MMU_ACCESS_FLASH) -#define VADDR1_START_ADDR IRAM0_CACHE_ADDRESS_LOW -#define PRO_IRAM0_FIRST_USABLE_PAGE (IROM0_PAGES_START) -#define VADDR0_START_ADDR (SOC_DROM_LOW + (DROM0_PAGES_START * SPI_FLASH_MMU_PAGE_SIZE)) -#endif - -#define IROM0_PAGES_NUM (IROM0_PAGES_END - IROM0_PAGES_START) -#define DROM0_PAGES_NUM (DROM0_PAGES_END - DROM0_PAGES_START) -#define PAGES_LIMIT (IROM0_PAGES_END > DROM0_PAGES_END ? IROM0_PAGES_END:DROM0_PAGES_END) -#define VADDR1_FIRST_USABLE_ADDR SOC_IROM_LOW +#define IROM0_PAGES_NUM (SOC_MMU_IROM0_PAGES_END - SOC_MMU_IROM0_PAGES_START) +#define DROM0_PAGES_NUM (SOC_MMU_DROM0_PAGES_END - SOC_MMU_DROM0_PAGES_START) +#define PAGES_LIMIT ((SOC_MMU_IROM0_PAGES_END > SOC_MMU_DROM0_PAGES_END) ? SOC_MMU_IROM0_PAGES_END:SOC_MMU_DROM0_PAGES_END) #if !CONFIG_SPI_FLASH_ROM_IMPL @@ -119,33 +79,33 @@ typedef struct mmap_entry_{ static LIST_HEAD(mmap_entries_head, mmap_entry_) s_mmap_entries_head = LIST_HEAD_INITIALIZER(s_mmap_entries_head); -static uint8_t s_mmap_page_refcnt[REGIONS_COUNT * PAGES_PER_REGION] = {0}; +static uint8_t s_mmap_page_refcnt[SOC_MMU_REGIONS_COUNT * SOC_MMU_PAGES_PER_REGION] = {0}; static uint32_t s_mmap_last_handle = 0; static void IRAM_ATTR spi_flash_mmap_init(void) { - if (s_mmap_page_refcnt[DROM0_PAGES_START] != 0) { + if (s_mmap_page_refcnt[SOC_MMU_DROM0_PAGES_START] != 0) { return; /* mmap data already initialised */ } DPORT_INTERRUPT_DISABLE(); - for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) { - uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]); + for (int i = 0; i < SOC_MMU_REGIONS_COUNT * SOC_MMU_PAGES_PER_REGION; ++i) { + uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]); #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 uint32_t entry_app = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]); if (entry_pro != entry_app) { // clean up entries used by boot loader - entry_pro = INVALID_ENTRY_VAL; - DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; + entry_pro = SOC_MMU_INVALID_ENTRY_VAL; + SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i] = SOC_MMU_INVALID_ENTRY_VAL; } #endif - if ((entry_pro & INVALID_ENTRY_VAL) == 0 && (i == DROM0_PAGES_START || i == PRO_IRAM0_FIRST_USABLE_PAGE || entry_pro != 0)) { + if ((entry_pro & SOC_MMU_INVALID_ENTRY_VAL) == 0 && (i == SOC_MMU_DROM0_PAGES_START || i == SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE || entry_pro != 0)) { s_mmap_page_refcnt[i] = 1; } else { - DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; + SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i] = SOC_MMU_INVALID_ENTRY_VAL; #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 - DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; + DPORT_APP_FLASH_MMU_TABLE[i] = SOC_MMU_INVALID_ENTRY_VAL; #endif } } @@ -156,14 +116,14 @@ static void IRAM_ATTR get_mmu_region(spi_flash_mmap_memory_t memory, int* out_be { if (memory == SPI_FLASH_MMAP_DATA) { // Vaddr0 - *out_begin = DROM0_PAGES_START; + *out_begin = SOC_MMU_DROM0_PAGES_START; *out_size = DROM0_PAGES_NUM; - *region_addr = VADDR0_START_ADDR; + *region_addr = SOC_MMU_VADDR0_START_ADDR; } else { // only part of VAddr1 is usable, so adjust for that - *out_begin = PRO_IRAM0_FIRST_USABLE_PAGE; - *out_size = IROM0_PAGES_END - *out_begin; - *region_addr = VADDR1_FIRST_USABLE_ADDR; + *out_begin = SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE; + *out_size = SOC_MMU_IROM0_PAGES_END - *out_begin; + *region_addr = SOC_MMU_VADDR1_FIRST_USABLE_ADDR; } } @@ -238,9 +198,9 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp int pos; DPORT_INTERRUPT_DISABLE(); for (pos = start; pos < start + page_count; ++pos, ++pageno) { - int table_val = (int) DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[pos]); + int table_val = (int) DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[pos]); uint8_t refcnt = s_mmap_page_refcnt[pos]; - if (refcnt != 0 && table_val != PAGE_IN_FLASH(pages[pageno])) { + if (refcnt != 0 && table_val != SOC_MMU_PAGE_IN_FLASH(pages[pageno])) { break; } } @@ -261,23 +221,23 @@ esp_err_t IRAM_ATTR spi_flash_mmap_pages(const int *pages, size_t page_count, sp DPORT_INTERRUPT_DISABLE(); for (int i = start; i != start + page_count; ++i, ++pageno) { // sanity check: we won't reconfigure entries with non-zero reference count - uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]); + uint32_t entry_pro = DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]); #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 uint32_t entry_app = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_APP_FLASH_MMU_TABLE[i]); #endif assert(s_mmap_page_refcnt[i] == 0 || - (entry_pro == PAGE_IN_FLASH(pages[pageno]) + (entry_pro == SOC_MMU_PAGE_IN_FLASH(pages[pageno]) #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 - && entry_app == PAGE_IN_FLASH(pages[pageno]) + && entry_app == SOC_MMU_PAGE_IN_FLASH(pages[pageno]) #endif )); if (s_mmap_page_refcnt[i] == 0) { - if (entry_pro != PAGE_IN_FLASH(pages[pageno]) + if (entry_pro != SOC_MMU_PAGE_IN_FLASH(pages[pageno]) #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 - || entry_app != PAGE_IN_FLASH(pages[pageno]) + || entry_app != SOC_MMU_PAGE_IN_FLASH(pages[pageno]) #endif ) { - DPORT_PRO_FLASH_MMU_TABLE[i] = PAGE_IN_FLASH(pages[pageno]); + SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i] = SOC_MMU_PAGE_IN_FLASH(pages[pageno]); #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 DPORT_APP_FLASH_MMU_TABLE[i] = pages[pageno]; #endif @@ -338,9 +298,9 @@ void IRAM_ATTR spi_flash_munmap(spi_flash_mmap_handle_t handle) for (int i = it->page; i < it->page + it->count; ++i) { assert(s_mmap_page_refcnt[i] > 0); if (--s_mmap_page_refcnt[i] == 0) { - DPORT_PRO_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; + SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i] = SOC_MMU_INVALID_ENTRY_VAL; #if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32 - DPORT_APP_FLASH_MMU_TABLE[i] = INVALID_ENTRY_VAL; + DPORT_APP_FLASH_MMU_TABLE[i] = SOC_MMU_INVALID_ENTRY_VAL; #endif } } @@ -366,7 +326,7 @@ static uint32_t IRAM_ATTR NOINLINE_ATTR spi_flash_protected_read_mmu_entry(int i { uint32_t value; spi_flash_disable_interrupts_caches_and_other_cpu(); - value = DPORT_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[index]); + value = DPORT_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[index]); spi_flash_enable_interrupts_caches_and_other_cpu(); return value; } @@ -379,7 +339,7 @@ void spi_flash_mmap_dump(void) for (it = LIST_FIRST(&s_mmap_entries_head); it != NULL; it = LIST_NEXT(it, entries)) { printf("handle=%d page=%d count=%d\n", it->handle, it->page, it->count); } - for (int i = 0; i < REGIONS_COUNT * PAGES_PER_REGION; ++i) { + for (int i = 0; i < SOC_MMU_REGIONS_COUNT * SOC_MMU_PAGES_PER_REGION; ++i) { if (s_mmap_page_refcnt[i] != 0) { uint32_t paddr = spi_flash_protected_read_mmu_entry(i); printf("page %d: refcnt=%d paddr=%d\n", i, (int) s_mmap_page_refcnt[i], paddr); @@ -398,7 +358,7 @@ uint32_t IRAM_ATTR spi_flash_mmap_get_free_pages(spi_flash_mmap_memory_t memory) get_mmu_region(memory,®ion_begin,®ion_size,®ion_addr); DPORT_INTERRUPT_DISABLE(); for (int i = region_begin; i < region_begin + region_size; ++i) { - if (s_mmap_page_refcnt[i] == 0 && DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]) == INVALID_ENTRY_VAL) { + if (s_mmap_page_refcnt[i] == 0 && DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]) == SOC_MMU_INVALID_ENTRY_VAL) { count++; } } @@ -412,16 +372,13 @@ size_t spi_flash_cache2phys(const void *cached) intptr_t c = (intptr_t)cached; size_t cache_page; int offset = 0; -#if !CONFIG_IDF_TARGET_ESP32C3 - if (c >= VADDR1_START_ADDR && c < VADDR1_FIRST_USABLE_ADDR) { -#else - if (c >= SOC_IRAM_LOW && c < VADDR1_FIRST_USABLE_ADDR) { -#endif + if (c >= SOC_MMU_VADDR1_START_ADDR && c < SOC_MMU_VADDR1_FIRST_USABLE_ADDR) { /* IRAM address, doesn't map to flash */ return SPI_FLASH_CACHE2PHYS_FAIL; - } else if (c < VADDR1_FIRST_USABLE_ADDR) { + } + if (c < SOC_MMU_VADDR1_FIRST_USABLE_ADDR) { /* expect cache is in DROM */ - cache_page = (c - VADDR0_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + DROM0_PAGES_START; + cache_page = (c - SOC_MMU_VADDR0_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_DROM0_PAGES_START; #if CONFIG_SPIRAM_RODATA if (c >= (uint32_t)&_rodata_reserved_start && c <= (uint32_t)&_rodata_reserved_end) { offset = rodata_flash2spiram_offset(); @@ -429,7 +386,7 @@ size_t spi_flash_cache2phys(const void *cached) #endif } else { /* expect cache is in IROM */ - cache_page = (c - VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + IROM0_PAGES_START; + cache_page = (c - SOC_MMU_VADDR1_START_ADDR) / SPI_FLASH_MMU_PAGE_SIZE + SOC_MMU_IROM0_PAGES_START; #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS if (c >= (uint32_t)&_instruction_reserved_start && c <= (uint32_t)&_instruction_reserved_end) { offset = instruction_flash2spiram_offset(); @@ -442,11 +399,11 @@ size_t spi_flash_cache2phys(const void *cached) return SPI_FLASH_CACHE2PHYS_FAIL; } uint32_t phys_page = spi_flash_protected_read_mmu_entry(cache_page); - if (phys_page == INVALID_ENTRY_VAL) { + if (phys_page == SOC_MMU_INVALID_ENTRY_VAL) { /* page is not mapped */ return SPI_FLASH_CACHE2PHYS_FAIL; } - uint32_t phys_offs = ((phys_page & MMU_ADDR_MASK) + offset) * SPI_FLASH_MMU_PAGE_SIZE; + uint32_t phys_offs = ((phys_page & SOC_MMU_ADDR_MASK) + offset) * SPI_FLASH_MMU_PAGE_SIZE; return phys_offs | (c & (SPI_FLASH_MMU_PAGE_SIZE-1)); } @@ -457,25 +414,25 @@ const void *IRAM_ATTR spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memo intptr_t base; if (memory == SPI_FLASH_MMAP_DATA) { - start = DROM0_PAGES_START; - end = DROM0_PAGES_END; - base = VADDR0_START_ADDR; - page_delta = DROM0_PAGES_START > IROM0_PAGES_START ? DROM0_PAGES_START : 0; + start = SOC_MMU_DROM0_PAGES_START; + end = SOC_MMU_DROM0_PAGES_END; + base = SOC_MMU_VADDR0_START_ADDR; + page_delta = SOC_MMU_DROM0_PAGES_START; } else { - start = PRO_IRAM0_FIRST_USABLE_PAGE; - end = IROM0_PAGES_END; - base = VADDR1_START_ADDR; - page_delta = DROM0_PAGES_START > IROM0_PAGES_START ? 0: IROM0_PAGES_START; + start = SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE; + end = SOC_MMU_IROM0_PAGES_END; + base = SOC_MMU_VADDR1_START_ADDR; + page_delta = SOC_MMU_IROM0_PAGES_START; } spi_flash_disable_interrupts_caches_and_other_cpu(); DPORT_INTERRUPT_DISABLE(); for (int i = start; i < end; i++) { - uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]); + uint32_t mmu_value = DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]); #if CONFIG_SPIRAM_FETCH_INSTRUCTIONS if (phys_page >= instruction_flash_start_page_get() && phys_page <= instruction_flash_end_page_get()) { if (mmu_value & MMU_ACCESS_SPIRAM) { mmu_value += instruction_flash2spiram_offset(); - mmu_value = (mmu_value & MMU_ADDR_MASK) | MMU_ACCESS_FLASH; + mmu_value = (mmu_value & SOC_MMU_ADDR_MASK) | MMU_ACCESS_FLASH; } } #endif @@ -483,11 +440,11 @@ const void *IRAM_ATTR spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memo if (phys_page >= rodata_flash_start_page_get() && phys_page <= rodata_flash_start_page_get()) { if (mmu_value & MMU_ACCESS_SPIRAM) { mmu_value += rodata_flash2spiram_offset(); - mmu_value = (mmu_value & MMU_ADDR_MASK) | MMU_ACCESS_FLASH; + mmu_value = (mmu_value & SOC_MMU_ADDR_MASK) | MMU_ACCESS_FLASH; } } #endif - if (mmu_value == PAGE_IN_FLASH(phys_page)) { + if (mmu_value == SOC_MMU_PAGE_IN_FLASH(phys_page)) { i -= page_delta; intptr_t cache_page = base + (SPI_FLASH_MMU_PAGE_SIZE * i); DPORT_INTERRUPT_RESTORE(); @@ -507,22 +464,22 @@ static bool IRAM_ATTR is_page_mapped_in_cache(uint32_t phys_page, const void **o *out_ptr = NULL; /* SPI_FLASH_MMAP_DATA */ - start[0] = DROM0_PAGES_START; - end[0] = DROM0_PAGES_END; + start[0] = SOC_MMU_DROM0_PAGES_START; + end[0] = SOC_MMU_DROM0_PAGES_END; /* SPI_FLASH_MMAP_INST */ - start[1] = PRO_IRAM0_FIRST_USABLE_PAGE; - end[1] = IROM0_PAGES_END; + start[1] = SOC_MMU_PRO_IRAM0_FIRST_USABLE_PAGE; + end[1] = SOC_MMU_IROM0_PAGES_END; DPORT_INTERRUPT_DISABLE(); for (int j = 0; j < 2; j++) { for (int i = start[j]; i < end[j]; i++) { - if (DPORT_SEQUENCE_REG_READ((uint32_t)&DPORT_PRO_FLASH_MMU_TABLE[i]) == PAGE_IN_FLASH(phys_page)) { + if (DPORT_SEQUENCE_REG_READ((uint32_t)&SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[i]) == SOC_MMU_PAGE_IN_FLASH(phys_page)) { #if !CONFIG_IDF_TARGET_ESP32 if (j == 0) { /* SPI_FLASH_MMAP_DATA */ - *out_ptr = (const void *)(VADDR0_START_ADDR + SPI_FLASH_MMU_PAGE_SIZE * (i - start[0])); + *out_ptr = (const void *)(SOC_MMU_VADDR0_START_ADDR + SPI_FLASH_MMU_PAGE_SIZE * (i - start[0])); } else { /* SPI_FLASH_MMAP_INST */ - *out_ptr = (const void *)(VADDR1_FIRST_USABLE_ADDR + SPI_FLASH_MMU_PAGE_SIZE * (i - start[1])); + *out_ptr = (const void *)(SOC_MMU_VADDR1_FIRST_USABLE_ADDR + SPI_FLASH_MMU_PAGE_SIZE * (i - start[1])); } #endif DPORT_INTERRUPT_RESTORE();