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fix ULP FSM reg ops with addr > 0xFF
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213504238f
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07332abbaa
@ -331,7 +331,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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*/
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*/
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.addr = ((reg) / sizeof(uint32_t)) & 0xff, \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.data = val, \
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.data = val, \
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.low = low_bit, \
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.low = low_bit, \
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@ -345,7 +345,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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*/
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*/
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.addr = ((reg) / sizeof(uint32_t)) & 0xff, \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.unused = 0, \
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.unused = 0, \
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.low = low_bit, \
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.low = low_bit, \
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@ -319,7 +319,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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*/
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*/
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.addr = ((reg) / sizeof(uint32_t)) & 0xff, \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.data = val, \
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.data = val, \
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.low = low_bit, \
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.low = low_bit, \
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@ -333,7 +333,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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*/
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*/
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.addr = ((reg) / sizeof(uint32_t)) & 0xff, \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.unused = 0, \
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.unused = 0, \
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.low = low_bit, \
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.low = low_bit, \
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@ -319,7 +319,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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*/
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*/
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.addr = ((reg) / sizeof(uint32_t)) & 0xff, \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.data = val, \
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.data = val, \
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.low = low_bit, \
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.low = low_bit, \
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@ -333,7 +333,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg)
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, SENS_, and RTC_I2C peripheral registers.
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*/
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*/
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.addr = ((reg) / sizeof(uint32_t)) & 0xff, \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.unused = 0, \
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.unused = 0, \
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.low = low_bit, \
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.low = low_bit, \
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