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fix(esp_rom): fix esp32c6, esp32h2 hp_regi2c ops data conflict with phy ops

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wuzhenghui 2023-08-18 15:16:02 +08:00 committed by loutianhao
parent d2730608d2
commit 05cd295a28
3 changed files with 120 additions and 138 deletions
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110
components/esp_rom/patches/esp_rom_hp_regi2c_esp32c6.c
View File

@ -19,11 +19,19 @@
* PMU - 0x6d - BIT8 * PMU - 0x6d - BIT8
*/ */
#define REGI2C_ULP_CAL_DEVICE_EN (BIT(6) << 4) #define REGI2C_BIAS_MST_SEL (BIT(8))
#define REGI2C_SAR_I2C_DEVICE_EN (BIT(7) << 4) #define REGI2C_BBPLL_MST_SEL (BIT(9))
#define REGI2C_BBPLL_DEVICE_EN (BIT(5) << 4) #define REGI2C_ULP_CAL_MST_SEL (BIT(10))
#define REGI2C_BIAS_DEVICE_EN (BIT(4) << 4) #define REGI2C_SAR_I2C_MST_SEL (BIT(11))
#define REGI2C_DIG_REG_DEVICE_EN (BIT(8) << 4) #define REGI2C_DIG_REG_MST_SEL (BIT(12))
#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_ANA_MST_ANA_CONF1_M)
#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_ANA_MST_ANA_CONF1_M)
#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_ANA_MST_ANA_CONF1_M)
#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_ANA_MST_ANA_CONF1_M)
#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_ANA_MST_ANA_CONF1_M)
#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
#define REGI2C_RTC_BUSY (BIT(25)) #define REGI2C_RTC_BUSY (BIT(25))
#define REGI2C_RTC_BUSY_M (BIT(25)) #define REGI2C_RTC_BUSY_M (BIT(25))
@ -74,69 +82,51 @@ uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add
void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl"))); void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl"))); void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
static IRAM_ATTR void regi2c_enable_block(uint8_t block) static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
{ {
uint32_t i2c_sel = 0;
REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M); REG_SET_BIT(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
REG_SET_FIELD(I2C_ANA_MST_ANA_CONF2_REG, I2C_ANA_MST_ANA_CONF2, 0);
/* Before config I2C register, enable corresponding slave. */ /* Before config I2C register, enable corresponding slave. */
switch (block) { switch (block) {
case REGI2C_BBPLL : case REGI2C_BBPLL :
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK);
break; break;
case REGI2C_BIAS : case REGI2C_BIAS :
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK);
break; break;
case REGI2C_DIG_REG: case REGI2C_DIG_REG:
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK);
break; break;
case REGI2C_ULP_CAL: case REGI2C_ULP_CAL:
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK);
break; break;
case REGI2C_SAR_I2C: case REGI2C_SAR_I2C:
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK);
break; break;
default:
return;
} }
}
static IRAM_ATTR void regi2c_disable_block(uint8_t block) return (uint8_t)(i2c_sel ? 0: 1);
{
switch (block) {
case REGI2C_BBPLL :
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN);
break;
case REGI2C_BIAS :
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
break;
case REGI2C_DIG_REG:
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_DEVICE_EN);
break;
case REGI2C_ULP_CAL:
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);
break;
case REGI2C_SAR_I2C:
REG_SET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN);
break;
default:
return;
}
} }
uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add) uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
{ {
regi2c_enable_block(block);
(void)host_id; (void)host_id;
uint8_t i2c_sel = regi2c_enable_block(block);
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA); uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
regi2c_disable_block(block);
return ret; return ret;
} }
@ -144,48 +134,48 @@ uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_a
uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
{ {
assert(msb - lsb < 8); assert(msb - lsb < 8);
regi2c_enable_block(block); uint8_t i2c_sel = regi2c_enable_block(block);
(void)host_id; (void)host_id;
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA); uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
regi2c_disable_block(block);
return ret; return ret;
} }
void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
{ {
(void)host_id; (void)host_id;
regi2c_enable_block(block); uint8_t i2c_sel = regi2c_enable_block(block);
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
| (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
regi2c_disable_block(block);
} }
void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
{ {
(void)host_id; (void)host_id;
assert(msb - lsb < 8); assert(msb - lsb < 8);
regi2c_enable_block(block); uint8_t i2c_sel = regi2c_enable_block(block);
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
/*Read the i2c bus register*/ /*Read the i2c bus register*/
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
temp = REG_GET_FIELD(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA); temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
/*Write the i2c bus register*/ /*Write the i2c bus register*/
temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
@ -193,8 +183,6 @@ void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t re
| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
| ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
REG_WRITE(I2C_ANA_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_ANA_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
regi2c_disable_block(block);
} }

126
components/esp_rom/patches/esp_rom_regi2c_esp32h2.c
View File

@ -19,11 +19,20 @@
* SAR - 0x69 - BIT7 * SAR - 0x69 - BIT7
* PMU - 0x6d - BIT8 * PMU - 0x6d - BIT8
*/ */
#define REGI2C_ULP_CAL_DEVICE_EN (BIT(6) << 4)
#define REGI2C_SAR_I2C_DEVICE_EN (BIT(7) << 4) #define REGI2C_BIAS_MST_SEL (BIT(8))
#define REGI2C_BBPLL_DEVICE_EN (BIT(5) << 4) #define REGI2C_BBPLL_MST_SEL (BIT(9))
#define REGI2C_BIAS_DEVICE_EN (BIT(4) << 4) #define REGI2C_ULP_CAL_MST_SEL (BIT(10))
#define REGI2C_PMU_DEVICE_EN (BIT(8) << 4) #define REGI2C_SAR_I2C_MST_SEL (BIT(11))
#define REGI2C_DIG_REG_MST_SEL (BIT(12))
#define REGI2C_BIAS_RD_MASK (~BIT(6) & I2C_MST_ANA_CONF1_M)
#define REGI2C_BBPLL_RD_MASK (~BIT(7) & I2C_MST_ANA_CONF1_M)
#define REGI2C_ULP_CAL_RD_MASK (~BIT(8) & I2C_MST_ANA_CONF1_M)
#define REGI2C_SAR_I2C_RD_MASK (~BIT(9) & I2C_MST_ANA_CONF1_M)
#define REGI2C_DIG_REG_RD_MASK (~BIT(10) & I2C_MST_ANA_CONF1_M)
#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
#define REGI2C_RTC_BUSY (BIT(25)) #define REGI2C_RTC_BUSY (BIT(25))
#define REGI2C_RTC_BUSY_M (BIT(25)) #define REGI2C_RTC_BUSY_M (BIT(25))
@ -69,116 +78,103 @@
/* SLAVE END */ /* SLAVE END */
static IRAM_ATTR void regi2c_enable_block(uint8_t block) uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl")));
uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl")));
void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
{ {
uint32_t i2c_sel = 0;
REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN); REG_SET_BIT(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
REG_SET_FIELD(I2C_MST_ANA_CONF2_REG, I2C_MST_ANA_CONF2, 0);
/* Before config I2C register, enable corresponding slave. */ /* Before config I2C register, enable corresponding slave. */
switch (block) { switch (block) {
case REGI2C_BBPLL : case REGI2C_BBPLL :
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK);
break; break;
case REGI2C_BIAS : case REGI2C_BIAS :
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
break; REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK);
case REGI2C_PMU :
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_PMU_DEVICE_EN);
break;
case REGI2C_ULP_CAL:
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN);
break;
case REGI2C_SAR_I2C:
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN);
break;
default:
return;
}
}
static IRAM_ATTR void regi2c_disable_block(uint8_t block)
{
switch (block) {
case REGI2C_BBPLL :
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BBPLL_DEVICE_EN);
break;
case REGI2C_BIAS :
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_BIAS_DEVICE_EN);
break; break;
case REGI2C_PMU: case REGI2C_PMU:
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_PMU_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK);
break; break;
case REGI2C_ULP_CAL: case REGI2C_ULP_CAL:
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK);
break; break;
case REGI2C_SAR_I2C: case REGI2C_SAR_I2C:
REG_SET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_DEVICE_EN); i2c_sel = REG_GET_BIT(I2C_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
REG_WRITE(I2C_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK);
break; break;
default:
return;
} }
return (uint8_t)(i2c_sel ? 0: 1);
} }
uint8_t IRAM_ATTR esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
{ {
regi2c_enable_block(block);
(void)host_id; (void)host_id;
uint8_t i2c_sel = regi2c_enable_block(block);
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
uint8_t ret = REG_GET_FIELD(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA); uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
regi2c_disable_block(block);
return ret; return ret;
} }
uint8_t IRAM_ATTR esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
{ {
assert(msb - lsb < 8); assert(msb - lsb < 8);
regi2c_enable_block(block); uint8_t i2c_sel = regi2c_enable_block(block);
(void)host_id; (void)host_id;
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
uint32_t data = REG_GET_FIELD(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA); uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1)))); uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
regi2c_disable_block(block);
return ret; return ret;
} }
void IRAM_ATTR esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
{ {
(void)host_id; (void)host_id;
regi2c_enable_block(block); uint8_t i2c_sel = regi2c_enable_block(block);
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register; | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
| (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
regi2c_disable_block(block);
} }
void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
{ {
(void)host_id; (void)host_id;
assert(msb - lsb < 8); assert(msb - lsb < 8);
regi2c_enable_block(block); uint8_t i2c_sel = regi2c_enable_block(block);
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
/*Read the i2c bus register*/ /*Read the i2c bus register*/
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S) uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S; | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
temp = REG_GET_FIELD(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_DATA); temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
/*Write the i2c bus register*/ /*Write the i2c bus register*/
temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1))); temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp; temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
@ -186,8 +182,6 @@ void IRAM_ATTR esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t
| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S) | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
| ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S); | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
REG_WRITE(I2C_MST_I2C0_CTRL_REG, temp); REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
while (REG_GET_BIT(I2C_MST_I2C0_CTRL_REG, REGI2C_RTC_BUSY)); while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
regi2c_disable_block(block);
} }

22
components/soc/esp32c6/include/soc/i2c_ana_mst_reg.h
View File

@ -104,44 +104,44 @@ extern "C" {
#define I2C_ANA_MST_BURST_DONE_S 0 #define I2C_ANA_MST_BURST_DONE_S 0
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18) #define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
/* I2C_MST_ANA_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/ /*description: .*/
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF #define I2C_ANA_MST_ANA_STATUS0 0x000000FF
#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_MST_ANA_STATUS0_V)<<(I2C_MST_ANA_STATUS0_S)) #define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S))
#define I2C_ANA_MST_ANA_STATUS0_V 0xFF #define I2C_ANA_MST_ANA_STATUS0_V 0xFF
#define I2C_ANA_MST_ANA_STATUS0_S 24 #define I2C_ANA_MST_ANA_STATUS0_S 24
/* I2C_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */ /* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
/*description: .*/ /*description: .*/
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
#define I2C_ANA_MST_ANA_CONF0_M ((I2C_MST_ANA_CONF0_V)<<(I2C_MST_ANA_CONF0_S)) #define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF #define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF
#define I2C_ANA_MST_ANA_CONF0_S 0 #define I2C_ANA_MST_ANA_CONF0_S 0
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C) #define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C)
/* I2C_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/ /*description: .*/
#define I2C_ANA_MST_ANA_STATUS1 0x000000FF #define I2C_ANA_MST_ANA_STATUS1 0x000000FF
#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_MST_ANA_STATUS1_V)<<(I2C_MST_ANA_STATUS1_S)) #define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S))
#define I2C_ANA_MST_ANA_STATUS1_V 0xFF #define I2C_ANA_MST_ANA_STATUS1_V 0xFF
#define I2C_ANA_MST_ANA_STATUS1_S 24 #define I2C_ANA_MST_ANA_STATUS1_S 24
/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */ /* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
/*description: .*/ /*description: .*/
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
#define I2C_ANA_MST_ANA_CONF1_M ((I2C_MST_ANA_CONF1_V)<<(I2C_MST_ANA_CONF1_S)) #define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF #define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF
#define I2C_ANA_MST_ANA_CONF1_S 0 #define I2C_ANA_MST_ANA_CONF1_S 0
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20) #define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
/* I2C_MST_ANA_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ /* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
/*description: .*/ /*description: .*/
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF #define I2C_ANA_MST_ANA_STATUS2 0x000000FF
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_MST_ANA_STATUS2_V)<<(I2C_MST_ANA_STATUS2_S)) #define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF #define I2C_ANA_MST_ANA_STATUS2_V 0xFF
#define I2C_ANA_MST_ANA_STATUS2_S 24 #define I2C_ANA_MST_ANA_STATUS2_S 24
/* I2C_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */ /* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
/*description: .*/ /*description: .*/
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF #define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
#define I2C_ANA_MST_ANA_CONF2_M ((I2C_MST_ANA_CONF2_V)<<(I2C_MST_ANA_CONF2_S)) #define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF #define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF
#define I2C_ANA_MST_ANA_CONF2_S 0 #define I2C_ANA_MST_ANA_CONF2_S 0