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Merge branch 'bugfix/fix_chip_broken_bug_in_monitor_mode_S2_v4.2' into 'release/v4.2'
pm: fix RTC IO and MEM issues under high temperature(v4.2) See merge request espressif/esp-idf!24252
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058fd7396b
@ -115,12 +115,13 @@ set sleep_init default param
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*/
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*/
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#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6
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#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6
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#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
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#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
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#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
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#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
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#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
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#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
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#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
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#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
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#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
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#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
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#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1
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#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1
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#define APLL_SDM_STOP_VAL_1 0x09
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#define APLL_SDM_STOP_VAL_1 0x09
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#define APLL_SDM_STOP_VAL_2_REV0 0x69
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#define APLL_SDM_STOP_VAL_2_REV0 0x69
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#define APLL_SDM_STOP_VAL_2_REV1 0x49
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#define APLL_SDM_STOP_VAL_2_REV1 0x49
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@ -655,7 +656,7 @@ typedef struct {
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.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
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.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
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.dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \
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.dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \
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.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
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.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
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.rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \
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.rtc_dbias_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG)? RTC_CNTL_DBIAS_1V25 : RTC_CNTL_DBIAS_1V00, \
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.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
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.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
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.deep_slp_reject = 1, \
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.deep_slp_reject = 1, \
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.light_slp_reject = 1 \
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.light_slp_reject = 1 \
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@ -95,14 +95,13 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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} else {
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
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}
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}
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SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
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if (cfg.deep_slp) {
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if (cfg.deep_slp) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
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@ -115,7 +114,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
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phy_close_rf();
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phy_close_rf();
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}
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}
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} else {
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT);
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}
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}
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