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Merge 3eed53a071 into 59e1838270

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DarkZeros 2024-09-13 15:56:39 +05:30 committed by GitHub
commit 052ea108bb
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2 changed files with 37 additions and 10 deletions
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18
components/esp_hw_support/port/esp32/Kconfig.rtc
View File

@ -85,6 +85,24 @@ config RTC_CLK_CAL_CYCLES
In case more value will help improve the definition of the launch of the crystal.
If the crystal could not start, it will be switched to internal RC.
config RTC_CLK_SLEEP_CAL_CYCLES
int "Number of cycles to calibrate RTC_SLOW_CLK before sleep"
default 10
range 0 1000
help
Just before entering light/deep sleep, a small calibration is done
on the RTC_SLOW_CLK. Having a calibrated RTC_SLOW_CLK is required
in order to proper measure time while in sleep modes and allow proper
wake up from timers.
This option defaults to 10 cycles (around 300us) but can be lowered
down to 0 to avoid calibration, and take the previous one as valid.
It can be particularly useful when the RTC_SLOW_CLK calibration is
done by the APP code using various external sources like NTP
and comparing the long term drift of the clock, or when using a very
stable external oscillator.
It can also be interesting for reducing power usage in APPs that are
constantly entering light sleep.
config RTC_XTAL_CAL_RETRY
int "Number of attempts to repeat 32k XTAL calibration"
default 1

29
components/esp_hw_support/sleep_modes.c
View File

@ -128,7 +128,11 @@
#define ESP_SLEEP_WAIT_FLASH_READY_DEFAULT_DELAY_US 700
// Cycles for RTC Timer clock source (internal oscillator) calibrate
#ifndef CONFIG_RTC_CLK_SLEEP_CAL_CYCLES
#define RTC_CLK_SRC_CAL_CYCLES (10)
#else
#define RTC_CLK_SRC_CAL_CYCLES CONFIG_RTC_CLK_SLEEP_CAL_CYCLES
#endif
#define FAST_CLK_SRC_CAL_CYCLES (2048) /* ~ 127.4 us */
#ifdef CONFIG_IDF_TARGET_ESP32
@ -720,7 +724,22 @@ FORCE_INLINE_ATTR void misc_modules_wake_prepare(uint32_t pd_flags)
static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
{
// Calibrate rtc fast clock, only PMU supported chips sleep process is needed.
#if SOC_PMU_SUPPORTED
#if CONFIG_PM_ENABLE
if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp)
#endif
{
s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES);
}
#endif
// Calibrate rtc slow clock
if (RTC_CLK_SRC_CAL_CYCLES <= 0)
s_config.rtc_clk_cal_period = esp_clk_slowclk_cal_get();
return;
}
#ifdef CONFIG_ESP_SYSTEM_RTC_EXT_XTAL
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
uint64_t time_per_us = 1000000ULL;
@ -743,16 +762,6 @@ static IRAM_ATTR void sleep_low_power_clock_calibration(bool is_dslp)
esp_clk_slowclk_cal_set(s_config.rtc_clk_cal_period);
}
#endif
// Calibrate rtc fast clock, only PMU supported chips sleep process is needed.
#if SOC_PMU_SUPPORTED
#if CONFIG_PM_ENABLE
if ((s_lightsleep_cnt % CONFIG_PM_LIGHTSLEEP_RTC_OSC_CAL_INTERVAL == 0) || is_dslp)
#endif
{
s_config.fast_clk_cal_period = rtc_clk_cal(RTC_CAL_RC_FAST, FAST_CLK_SRC_CAL_CYCLES);
}
#endif
}