mirror of
https://github.com/espressif/esp-idf.git
synced 2024-10-05 20:47:46 -04:00
Merge branch 'feature/p4_rng' into 'master'
feat(esp_hw_support): brought up RNG on ESP32-P4 Closes IDF-6522 See merge request espressif/esp-idf!29614
This commit is contained in:
Aditya Patwardhan
commit
051048d261
@ -28,6 +28,9 @@
|
||||
#if (defined CONFIG_IDF_TARGET_ESP32C6 || defined CONFIG_IDF_TARGET_ESP32H2)
|
||||
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 16) // Keep the byte sampling frequency in the ~62KHz range which has been
|
||||
// tested.
|
||||
#elif CONFIG_IDF_TARGET_ESP32P4
|
||||
// bootloader tested with around 63 KHz bytes reading frequency
|
||||
#define RNG_CPU_WAIT_CYCLE_NUM (CPU_CLK_FREQ_MHZ_BTLD * 16)
|
||||
#else
|
||||
#define RNG_CPU_WAIT_CYCLE_NUM (80 * 32 * 2) /* extra factor of 2 is precautionary */
|
||||
#endif
|
||||
|
||||
@ -1,22 +1,101 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include "sdkconfig.h"
|
||||
#include "bootloader_random.h"
|
||||
#include "esp_log.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/adc_reg.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
#include "soc/regi2c_saradc.h"
|
||||
#include "soc/hp_sys_clkrst_reg.h"
|
||||
#include "soc/rtcadc_reg.h"
|
||||
#include "esp_private/regi2c_ctrl.h"
|
||||
#include "esp_rom_regi2c.h"
|
||||
|
||||
static const char *TAG = "bootloader_random";
|
||||
// TODO IDF-6497: once ADC API is supported, use the API instead of defining functions and constants here
|
||||
|
||||
#define I2C_SAR_ADC_INIT_CODE_VAL 2166
|
||||
|
||||
typedef struct {
|
||||
int atten;
|
||||
int channel;
|
||||
} pattern_item;
|
||||
|
||||
typedef struct {
|
||||
pattern_item item[4];
|
||||
} pattern_table;
|
||||
|
||||
static void adc1_fix_initcode_set(uint32_t initcode_value)
|
||||
{
|
||||
uint32_t msb = initcode_value >> 8;
|
||||
uint32_t lsb = initcode_value & 0xff;
|
||||
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_MSB, msb);
|
||||
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_SAR1_INIT_CODE_LSB, lsb);
|
||||
}
|
||||
|
||||
//total 4 tables
|
||||
static void hpadc_sar1_pattern_table_cfg(unsigned int table_idx, pattern_table table)
|
||||
{
|
||||
uint32_t wdata = 0;
|
||||
wdata = (table.item[0].channel << 20 | table.item[0].atten << 18 |
|
||||
table.item[1].channel << 14|table.item[1].atten << 12 |
|
||||
table.item[2].channel << 8 |table.item[2].atten << 6 |
|
||||
table.item[3].channel << 2 |table.item[3].atten);
|
||||
WRITE_PERI_REG(ADC_SAR1_PATT_TAB1_REG + table_idx * 4, wdata);
|
||||
}
|
||||
|
||||
void bootloader_random_enable(void)
|
||||
{
|
||||
// TODO: IDF-6522
|
||||
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
|
||||
pattern_table sar1_table[4] = {};
|
||||
uint32_t pattern_len = 0;
|
||||
|
||||
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_ADC_APB_CLK_EN);
|
||||
SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL23_REG, HP_SYS_CLKRST_REG_ADC_CLK_EN);
|
||||
|
||||
SET_PERI_REG_MASK(RTCADC_MEAS1_MUX_REG, RTCADC_SAR1_DIG_FORCE);
|
||||
SET_PERI_REG_MASK(PMU_RF_PWC_REG,PMU_XPD_PERIF_I2C);
|
||||
|
||||
uint32_t sar1_clk_div_num = GET_PERI_REG_BITS2((HP_SYS_CLKRST_PERI_CLK_CTRL24_REG),
|
||||
(HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_M),
|
||||
(HP_SYS_CLKRST_REG_ADC_SAR1_CLK_DIV_NUM_S));
|
||||
|
||||
SET_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE); //start force 1
|
||||
|
||||
adc1_fix_initcode_set(I2C_SAR_ADC_INIT_CODE_VAL);
|
||||
|
||||
// cfg pattern table
|
||||
sar1_table[0].item[0].channel = 10; //rand() % 6;
|
||||
sar1_table[0].item[0].atten = 3;
|
||||
sar1_table[0].item[1].channel = 10;
|
||||
sar1_table[0].item[1].atten = 3;
|
||||
sar1_table[0].item[2].channel = 10;
|
||||
sar1_table[0].item[2].atten = 3;
|
||||
sar1_table[0].item[3].channel = 10;
|
||||
sar1_table[0].item[3].atten = 3;
|
||||
|
||||
hpadc_sar1_pattern_table_cfg(0, sar1_table[0]);
|
||||
SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_SAR1_PATT_LEN, pattern_len, ADC_SAR1_PATT_LEN_S);
|
||||
|
||||
SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR1_FORCE, 3, ADC_XPD_SAR1_FORCE_S);
|
||||
SET_PERI_REG_BITS(ADC_CTRL_REG_REG, ADC_XPD_SAR2_FORCE, 3, ADC_XPD_SAR2_FORCE_S);
|
||||
|
||||
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, 1);
|
||||
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, 0);
|
||||
SET_PERI_REG_BITS(RTCADC_READER1_CTRL_REG, RTCADC_SAR1_EN_PAD_FORCE_ENABLE, 3, RTCADC_SAR1_EN_PAD_FORCE_ENABLE_S);
|
||||
|
||||
CLEAR_PERI_REG_MASK(ADC_CTRL_REG_REG, ADC_START_FORCE);
|
||||
SET_PERI_REG_MASK(ADC_CTRL2_REG, ADC_TIMER_EN);
|
||||
SET_PERI_REG_BITS(ADC_CTRL2_REG, ADC_TIMER_TARGET, sar1_clk_div_num * 25, ADC_TIMER_TARGET_S);
|
||||
|
||||
while (GET_PERI_REG_MASK(ADC_INT_RAW_REG, ADC_SAR1_DONE_INT_RAW) == 0) { }
|
||||
|
||||
SET_PERI_REG_MASK(ADC_INT_CLR_REG, ADC_APB_SARADC1_DONE_INT_CLR);
|
||||
}
|
||||
|
||||
void bootloader_random_disable(void)
|
||||
{
|
||||
// TODO: IDF-6522
|
||||
ESP_EARLY_LOGW(TAG, "bootloader_random_enable() has not been implemented yet");
|
||||
// No-op for now TODO IDF-6497
|
||||
// ADC should be set to defaults here, once ADC API is implemented
|
||||
// OR just keep this empty and let application continue to use RNG initialized by the bootloader
|
||||
}
|
||||
|
||||
@ -36,22 +36,13 @@
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32H2
|
||||
#define APB_CYCLE_WAIT_NUM (96 * 16) /* Same reasoning as for ESP32C6, but the CPU frequency on ESP32H2 is
|
||||
* 96MHz instead of 160 MHz */
|
||||
#elif defined CONFIG_IDF_TARGET_ESP32P4
|
||||
/* On ESP32P4, the RNG has been tested with around 75 KHz bytes reading frequency */
|
||||
#define APB_CYCLE_WAIT_NUM (CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ * 14)
|
||||
#else
|
||||
#define APB_CYCLE_WAIT_NUM (16)
|
||||
#endif
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
#include "esp_log.h"
|
||||
static const char *TAG = "hw_random";
|
||||
|
||||
uint32_t IRAM_ATTR esp_random(void)
|
||||
{
|
||||
// TODO: IDF-6522
|
||||
ESP_EARLY_LOGW(TAG, "esp_random() has not been implemented yet");
|
||||
return 0xDEADBEEF;
|
||||
}
|
||||
#else // !CONFIG_IDF_TARGET_ESP32P4
|
||||
|
||||
uint32_t IRAM_ATTR esp_random(void)
|
||||
{
|
||||
/* The PRNG which implements WDEV_RANDOM register gets 2 bits
|
||||
@ -61,7 +52,7 @@ uint32_t IRAM_ATTR esp_random(void)
|
||||
* clock cycles after reading previous word. This implementation may actually
|
||||
* wait a bit longer due to extra time spent in arithmetic and branch statements.
|
||||
*
|
||||
* As a (probably unncessary) precaution to avoid returning the
|
||||
* As a (probably unnecessary) precaution to avoid returning the
|
||||
* RNG state as-is, the result is XORed with additional
|
||||
* WDEV_RND_REG reads while waiting.
|
||||
*/
|
||||
@ -95,7 +86,6 @@ uint32_t IRAM_ATTR esp_random(void)
|
||||
last_ccount = ccount;
|
||||
return result ^ REG_READ(WDEV_RND_REG);
|
||||
}
|
||||
#endif //!CONFIG_IDF_TARGET_ESP32P4
|
||||
|
||||
void esp_fill_random(void *buf, size_t len)
|
||||
{
|
||||
|
||||
@ -461,11 +461,19 @@ void IRAM_ATTR call_start_cpu0(void)
|
||||
#endif //#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
|
||||
#endif //#if CONFIG_APP_BUILD_TYPE_RAM
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32P4
|
||||
#define RWDT_RESET RESET_REASON_CORE_RWDT
|
||||
#define MWDT_RESET RESET_REASON_CORE_MWDT
|
||||
#else
|
||||
#define RWDT_RESET RESET_REASON_CORE_RTC_WDT
|
||||
#define MWDT_RESET RESET_REASON_CORE_MWDT0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_BOOTLOADER_WDT_ENABLE
|
||||
// from panic handler we can be reset by RWDT or TG0WDT
|
||||
if (rst_reas[0] == RESET_REASON_CORE_RTC_WDT || rst_reas[0] == RESET_REASON_CORE_MWDT0
|
||||
if (rst_reas[0] == RWDT_RESET || rst_reas[0] == MWDT_RESET
|
||||
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
|
||||
|| rst_reas[1] == RESET_REASON_CORE_RTC_WDT || rst_reas[1] == RESET_REASON_CORE_MWDT0
|
||||
|| rst_reas[1] == RWDT_RESET || rst_reas[1] == MWDT_RESET
|
||||
#endif
|
||||
) {
|
||||
wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT();
|
||||
@ -595,7 +603,7 @@ void IRAM_ATTR call_start_cpu0(void)
|
||||
#elif CONFIG_IDF_TARGET_ESP32S3
|
||||
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN);
|
||||
#if SOC_APPCPU_HAS_CLOCK_GATING_BUG
|
||||
/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETING
|
||||
/* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING
|
||||
signals to ensure that the App core stops running in single-core mode. */
|
||||
REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL);
|
||||
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
|
||||
|
||||
@ -247,6 +247,10 @@ config SOC_SPI_FLASH_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RNG_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_GP_LDO_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -21,3 +21,19 @@
|
||||
#define I2C_SARADC_TSENS_DAC 0x6
|
||||
#define I2C_SARADC_TSENS_DAC_MSB 3
|
||||
#define I2C_SARADC_TSENS_DAC_LSB 0
|
||||
|
||||
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB 0
|
||||
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_MSB 7
|
||||
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_LSB 0
|
||||
|
||||
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB 1
|
||||
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_MSB 3
|
||||
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_LSB 0
|
||||
|
||||
#define I2C_SAR_ADC_ENT_VDD_GRP1 9
|
||||
#define I2C_SAR_ADC_ENT_VDD_GRP1_MSB 4
|
||||
#define I2C_SAR_ADC_ENT_VDD_GRP1_LSB 4
|
||||
|
||||
#define I2C_SAR_ADC_DTEST_VDD_GRP1 9
|
||||
#define I2C_SAR_ADC_DTEST_VDD_GRP1_MSB 3
|
||||
#define I2C_SAR_ADC_DTEST_VDD_GRP1_LSB 0
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@ -14,7 +14,7 @@ extern "C" {
|
||||
/** RTCADC_READER1_CTRL_REG register
|
||||
* Control the read operation of ADC1.
|
||||
*/
|
||||
#define RTCADC_READER1_CTRL_REG (DR_REG_RTCADC_BASE + 0x0)
|
||||
#define RTCADC_READER1_CTRL_REG (DR_REG_LP_ADC_BASE + 0x0)
|
||||
/** RTCADC_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
|
||||
* Clock divider.
|
||||
*/
|
||||
@ -47,7 +47,7 @@ extern "C" {
|
||||
/** RTCADC_MEAS1_CTRL2_REG register
|
||||
* ADC1 configuration registers.
|
||||
*/
|
||||
#define RTCADC_MEAS1_CTRL2_REG (DR_REG_RTCADC_BASE + 0xc)
|
||||
#define RTCADC_MEAS1_CTRL2_REG (DR_REG_LP_ADC_BASE + 0xc)
|
||||
/** RTCADC_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0;
|
||||
* SAR ADC1 data.
|
||||
*/
|
||||
@ -94,7 +94,7 @@ extern "C" {
|
||||
/** RTCADC_MEAS1_MUX_REG register
|
||||
* SAR ADC1 MUX register.
|
||||
*/
|
||||
#define RTCADC_MEAS1_MUX_REG (DR_REG_RTCADC_BASE + 0x10)
|
||||
#define RTCADC_MEAS1_MUX_REG (DR_REG_LP_ADC_BASE + 0x10)
|
||||
/** RTCADC_SAR1_DIG_FORCE : R/W; bitpos: [31]; default: 0;
|
||||
* 1: SAR ADC1 controlled by DIG ADC1 CTRL.
|
||||
*/
|
||||
@ -106,7 +106,7 @@ extern "C" {
|
||||
/** RTCADC_ATTEN1_REG register
|
||||
* ADC1 attenuation registers.
|
||||
*/
|
||||
#define RTCADC_ATTEN1_REG (DR_REG_RTCADC_BASE + 0x14)
|
||||
#define RTCADC_ATTEN1_REG (DR_REG_LP_ADC_BASE + 0x14)
|
||||
/** RTCADC_SAR1_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* 2-bit attenuation for each pad.
|
||||
*/
|
||||
@ -118,7 +118,7 @@ extern "C" {
|
||||
/** RTCADC_READER2_CTRL_REG register
|
||||
* Control the read operation of ADC2.
|
||||
*/
|
||||
#define RTCADC_READER2_CTRL_REG (DR_REG_RTCADC_BASE + 0x24)
|
||||
#define RTCADC_READER2_CTRL_REG (DR_REG_LP_ADC_BASE + 0x24)
|
||||
/** RTCADC_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2;
|
||||
* Clock divider.
|
||||
*/
|
||||
@ -158,7 +158,7 @@ extern "C" {
|
||||
/** RTCADC_MEAS2_CTRL1_REG register
|
||||
* ADC2 configuration registers.
|
||||
*/
|
||||
#define RTCADC_MEAS2_CTRL1_REG (DR_REG_RTCADC_BASE + 0x2c)
|
||||
#define RTCADC_MEAS2_CTRL1_REG (DR_REG_LP_ADC_BASE + 0x2c)
|
||||
/** RTCADC_SAR2_CNTL_STATE : RO; bitpos: [2:0]; default: 0;
|
||||
* saradc2_cntl_fsm.
|
||||
*/
|
||||
@ -191,7 +191,7 @@ extern "C" {
|
||||
/** RTCADC_MEAS2_CTRL2_REG register
|
||||
* ADC2 configuration registers.
|
||||
*/
|
||||
#define RTCADC_MEAS2_CTRL2_REG (DR_REG_RTCADC_BASE + 0x30)
|
||||
#define RTCADC_MEAS2_CTRL2_REG (DR_REG_LP_ADC_BASE + 0x30)
|
||||
/** RTCADC_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0;
|
||||
* SAR ADC2 data.
|
||||
*/
|
||||
@ -238,7 +238,7 @@ extern "C" {
|
||||
/** RTCADC_MEAS2_MUX_REG register
|
||||
* SAR ADC2 MUX register.
|
||||
*/
|
||||
#define RTCADC_MEAS2_MUX_REG (DR_REG_RTCADC_BASE + 0x34)
|
||||
#define RTCADC_MEAS2_MUX_REG (DR_REG_LP_ADC_BASE + 0x34)
|
||||
/** RTCADC_SAR2_PWDET_CCT : R/W; bitpos: [30:28]; default: 0;
|
||||
* SAR2_PWDET_CCT.
|
||||
*/
|
||||
@ -257,7 +257,7 @@ extern "C" {
|
||||
/** RTCADC_ATTEN2_REG register
|
||||
* ADC1 attenuation registers.
|
||||
*/
|
||||
#define RTCADC_ATTEN2_REG (DR_REG_RTCADC_BASE + 0x38)
|
||||
#define RTCADC_ATTEN2_REG (DR_REG_LP_ADC_BASE + 0x38)
|
||||
/** RTCADC_SAR2_ATTEN : R/W; bitpos: [31:0]; default: 4294967295;
|
||||
* 2-bit attenuation for each pad.
|
||||
*/
|
||||
@ -269,7 +269,7 @@ extern "C" {
|
||||
/** RTCADC_FORCE_WPD_SAR_REG register
|
||||
* In sleep, force to use rtc to control ADC
|
||||
*/
|
||||
#define RTCADC_FORCE_WPD_SAR_REG (DR_REG_RTCADC_BASE + 0x3c)
|
||||
#define RTCADC_FORCE_WPD_SAR_REG (DR_REG_LP_ADC_BASE + 0x3c)
|
||||
/** RTCADC_FORCE_XPD_SAR1 : R/W; bitpos: [1:0]; default: 0;
|
||||
* 2'b11:software control, force on. 2'b10:software control, force off. 2'b0x:hardware
|
||||
* control.
|
||||
@ -290,7 +290,7 @@ extern "C" {
|
||||
/** RTCADC_COCPU_INT_RAW_REG register
|
||||
* Interrupt raw registers.
|
||||
*/
|
||||
#define RTCADC_COCPU_INT_RAW_REG (DR_REG_RTCADC_BASE + 0x48)
|
||||
#define RTCADC_COCPU_INT_RAW_REG (DR_REG_LP_ADC_BASE + 0x48)
|
||||
/** RTCADC_COCPU_SARADC1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* ADC1 Conversion is done, int raw.
|
||||
*/
|
||||
@ -306,14 +306,14 @@ extern "C" {
|
||||
#define RTCADC_COCPU_SARADC2_INT_RAW_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC2_INT_RAW_S 1
|
||||
/** RTCADC_COCPU_SARADC1_ERROR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* An errro occurs from ADC1, int raw.
|
||||
* An error occurs from ADC1, int raw.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW (BIT(2))
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_M (RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S)
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_RAW_S 2
|
||||
/** RTCADC_COCPU_SARADC2_ERROR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0;
|
||||
* An errro occurs from ADC2, int raw.
|
||||
* An error occurs from ADC2, int raw.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW (BIT(3))
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_RAW_M (RTCADC_COCPU_SARADC2_ERROR_INT_RAW_V << RTCADC_COCPU_SARADC2_ERROR_INT_RAW_S)
|
||||
@ -337,7 +337,7 @@ extern "C" {
|
||||
/** RTCADC_INT_ENA_REG register
|
||||
* Interrupt enable registers.
|
||||
*/
|
||||
#define RTCADC_INT_ENA_REG (DR_REG_RTCADC_BASE + 0x4c)
|
||||
#define RTCADC_INT_ENA_REG (DR_REG_LP_ADC_BASE + 0x4c)
|
||||
/** RTCADC_COCPU_SARADC1_INT_ENA : R/WTC; bitpos: [0]; default: 0;
|
||||
* ADC1 Conversion is done, int enable.
|
||||
*/
|
||||
@ -353,14 +353,14 @@ extern "C" {
|
||||
#define RTCADC_COCPU_SARADC2_INT_ENA_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC2_INT_ENA_S 1
|
||||
/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA : R/WTC; bitpos: [2]; default: 0;
|
||||
* An errro occurs from ADC1, int enable.
|
||||
* An error occurs from ADC1, int enable.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA (BIT(2))
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S)
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_S 2
|
||||
/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA : R/WTC; bitpos: [3]; default: 0;
|
||||
* An errro occurs from ADC2, int enable.
|
||||
* An error occurs from ADC2, int enable.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA (BIT(3))
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_S)
|
||||
@ -384,7 +384,7 @@ extern "C" {
|
||||
/** RTCADC_INT_ST_REG register
|
||||
* Interrupt status registers.
|
||||
*/
|
||||
#define RTCADC_INT_ST_REG (DR_REG_RTCADC_BASE + 0x50)
|
||||
#define RTCADC_INT_ST_REG (DR_REG_LP_ADC_BASE + 0x50)
|
||||
/** RTCADC_COCPU_SARADC1_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* ADC1 Conversion is done, int status.
|
||||
*/
|
||||
@ -400,14 +400,14 @@ extern "C" {
|
||||
#define RTCADC_COCPU_SARADC2_INT_ST_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC2_INT_ST_S 1
|
||||
/** RTCADC_COCPU_SARADC1_ERROR_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* An errro occurs from ADC1, int status.
|
||||
* An error occurs from ADC1, int status.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST (BIT(2))
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_M (RTCADC_COCPU_SARADC1_ERROR_INT_ST_V << RTCADC_COCPU_SARADC1_ERROR_INT_ST_S)
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ST_S 2
|
||||
/** RTCADC_COCPU_SARADC2_ERROR_INT_ST : RO; bitpos: [3]; default: 0;
|
||||
* An errro occurs from ADC2, int status.
|
||||
* An error occurs from ADC2, int status.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ST (BIT(3))
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ST_M (RTCADC_COCPU_SARADC2_ERROR_INT_ST_V << RTCADC_COCPU_SARADC2_ERROR_INT_ST_S)
|
||||
@ -431,7 +431,7 @@ extern "C" {
|
||||
/** RTCADC_INT_CLR_REG register
|
||||
* Interrupt clear registers.
|
||||
*/
|
||||
#define RTCADC_INT_CLR_REG (DR_REG_RTCADC_BASE + 0x54)
|
||||
#define RTCADC_INT_CLR_REG (DR_REG_LP_ADC_BASE + 0x54)
|
||||
/** RTCADC_COCPU_SARADC1_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* ADC1 Conversion is done, int clear.
|
||||
*/
|
||||
@ -447,14 +447,14 @@ extern "C" {
|
||||
#define RTCADC_COCPU_SARADC2_INT_CLR_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC2_INT_CLR_S 1
|
||||
/** RTCADC_COCPU_SARADC1_ERROR_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* An errro occurs from ADC1, int clear.
|
||||
* An error occurs from ADC1, int clear.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR (BIT(2))
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_M (RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S)
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_CLR_S 2
|
||||
/** RTCADC_COCPU_SARADC2_ERROR_INT_CLR : WT; bitpos: [3]; default: 0;
|
||||
* An errro occurs from ADC2, int clear.
|
||||
* An error occurs from ADC2, int clear.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR (BIT(3))
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_CLR_M (RTCADC_COCPU_SARADC2_ERROR_INT_CLR_V << RTCADC_COCPU_SARADC2_ERROR_INT_CLR_S)
|
||||
@ -478,7 +478,7 @@ extern "C" {
|
||||
/** RTCADC_INT_ENA_W1TS_REG register
|
||||
* Interrupt enable assert registers.
|
||||
*/
|
||||
#define RTCADC_INT_ENA_W1TS_REG (DR_REG_RTCADC_BASE + 0x58)
|
||||
#define RTCADC_INT_ENA_W1TS_REG (DR_REG_LP_ADC_BASE + 0x58)
|
||||
/** RTCADC_COCPU_SARADC1_INT_ENA_W1TS : WT; bitpos: [0]; default: 0;
|
||||
* ADC1 Conversion is done, write 1 to assert int enable.
|
||||
*/
|
||||
@ -494,14 +494,14 @@ extern "C" {
|
||||
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TS_S 1
|
||||
/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS : WT; bitpos: [2]; default: 0;
|
||||
* An errro occurs from ADC1, write 1 to assert int enable.
|
||||
* An error occurs from ADC1, write 1 to assert int enable.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS (BIT(2))
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S)
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TS_S 2
|
||||
/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS : WT; bitpos: [3]; default: 0;
|
||||
* An errro occurs from ADC2, write 1 to assert int enable.
|
||||
* An error occurs from ADC2, write 1 to assert int enable.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS (BIT(3))
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TS_S)
|
||||
@ -525,7 +525,7 @@ extern "C" {
|
||||
/** RTCADC_INT_ENA_W1TC_REG register
|
||||
* Interrupt enable deassert registers.
|
||||
*/
|
||||
#define RTCADC_INT_ENA_W1TC_REG (DR_REG_RTCADC_BASE + 0x5c)
|
||||
#define RTCADC_INT_ENA_W1TC_REG (DR_REG_LP_ADC_BASE + 0x5c)
|
||||
/** RTCADC_COCPU_SARADC1_INT_ENA_W1TC : WT; bitpos: [0]; default: 0;
|
||||
* ADC1 Conversion is done, write 1 to deassert int enable.
|
||||
*/
|
||||
@ -541,14 +541,14 @@ extern "C" {
|
||||
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC2_INT_ENA_W1TC_S 1
|
||||
/** RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC : WT; bitpos: [2]; default: 0;
|
||||
* An errro occurs from ADC1, write 1 to deassert int enable.
|
||||
* An error occurs from ADC1, write 1 to deassert int enable.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC (BIT(2))
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S)
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_V 0x00000001U
|
||||
#define RTCADC_COCPU_SARADC1_ERROR_INT_ENA_W1TC_S 2
|
||||
/** RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC : WT; bitpos: [3]; default: 0;
|
||||
* An errro occurs from ADC2, write 1 to deassert int enable.
|
||||
* An error occurs from ADC2, write 1 to deassert int enable.
|
||||
*/
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC (BIT(3))
|
||||
#define RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_M (RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_V << RTCADC_COCPU_SARADC2_ERROR_INT_ENA_W1TC_S)
|
||||
@ -572,7 +572,7 @@ extern "C" {
|
||||
/** RTCADC_WAKEUP1_REG register
|
||||
* ADC1 wakeup configuration registers.
|
||||
*/
|
||||
#define RTCADC_WAKEUP1_REG (DR_REG_RTCADC_BASE + 0x60)
|
||||
#define RTCADC_WAKEUP1_REG (DR_REG_LP_ADC_BASE + 0x60)
|
||||
/** RTCADC_SAR1_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
|
||||
* Lower threshold.
|
||||
*/
|
||||
@ -612,7 +612,7 @@ extern "C" {
|
||||
/** RTCADC_WAKEUP2_REG register
|
||||
* ADC2 wakeup configuration registers.
|
||||
*/
|
||||
#define RTCADC_WAKEUP2_REG (DR_REG_RTCADC_BASE + 0x64)
|
||||
#define RTCADC_WAKEUP2_REG (DR_REG_LP_ADC_BASE + 0x64)
|
||||
/** RTCADC_SAR2_WAKEUP_TH_LOW : R/W; bitpos: [11:0]; default: 0;
|
||||
* Lower threshold.
|
||||
*/
|
||||
@ -652,7 +652,7 @@ extern "C" {
|
||||
/** RTCADC_WAKEUP_SEL_REG register
|
||||
* Wakeup source select register.
|
||||
*/
|
||||
#define RTCADC_WAKEUP_SEL_REG (DR_REG_RTCADC_BASE + 0x68)
|
||||
#define RTCADC_WAKEUP_SEL_REG (DR_REG_LP_ADC_BASE + 0x68)
|
||||
/** RTCADC_SAR_WAKEUP_SEL : R/W; bitpos: [0]; default: 0;
|
||||
* 0: ADC1. 1: ADC2.
|
||||
*/
|
||||
@ -664,7 +664,7 @@ extern "C" {
|
||||
/** RTCADC_SAR1_HW_WAKEUP_REG register
|
||||
* Hardware automatic sampling registers for wakeup function.
|
||||
*/
|
||||
#define RTCADC_SAR1_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x6c)
|
||||
#define RTCADC_SAR1_HW_WAKEUP_REG (DR_REG_LP_ADC_BASE + 0x6c)
|
||||
/** RTCADC_ADC1_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
|
||||
* Enable hardware automatic sampling.
|
||||
*/
|
||||
@ -683,7 +683,7 @@ extern "C" {
|
||||
/** RTCADC_SAR2_HW_WAKEUP_REG register
|
||||
* Hardware automatic sampling registers for wakeup function.
|
||||
*/
|
||||
#define RTCADC_SAR2_HW_WAKEUP_REG (DR_REG_RTCADC_BASE + 0x70)
|
||||
#define RTCADC_SAR2_HW_WAKEUP_REG (DR_REG_LP_ADC_BASE + 0x70)
|
||||
/** RTCADC_ADC2_HW_READ_EN_I : R/W; bitpos: [0]; default: 0;
|
||||
* Enable hardware automatic sampling.
|
||||
*/
|
||||
|
||||
@ -87,7 +87,7 @@
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
#define SOC_SPI_FLASH_SUPPORTED 1
|
||||
// #define SOC_TOUCH_SENSOR_SUPPORTED 1 //TODO: IDF-7477
|
||||
// #define SOC_RNG_SUPPORTED 1 //TODO: IDF-6522
|
||||
#define SOC_RNG_SUPPORTED 1
|
||||
#define SOC_GP_LDO_SUPPORTED 1 // General purpose LDO
|
||||
// #define SOC_PPA_SUPPORTED 1 //TODO: IDF-6878
|
||||
#define SOC_LIGHT_SLEEP_SUPPORTED 1
|
||||
|
||||
@ -9,6 +9,5 @@
|
||||
#include "soc.h"
|
||||
#include "soc/lpperi_reg.h"
|
||||
|
||||
//TODO: IDF-6522
|
||||
/* Hardware random number generator register */
|
||||
#define WDEV_RND_REG 0x600260b0
|
||||
#define WDEV_RND_REG 0x501101a4
|
||||
|
||||
Loading…
Reference in New Issue
Block a user