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ulp: fix I_{RD,WR}_REG definitions
- I_RD_REG used the wrong union member (.rd_reg) due to a copy-paste mistake - Peripheral register address in bits[7:0] should be given in words, not in bytes Fixes https://github.com/espressif/esp-idf/issues/297
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@ -307,7 +307,7 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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*/
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*/
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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#define I_WR_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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.addr = reg & 0xff, \
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.data = val, \
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.data = val, \
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.low = low_bit, \
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.low = low_bit, \
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@ -320,8 +320,8 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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* R0 = reg[high_bit : low_bit]
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* R0 = reg[high_bit : low_bit]
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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* This instruction can access RTC_CNTL_, RTC_IO_, and SENS_ peripheral registers.
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*/
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*/
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#define I_RD_REG(reg, low_bit, high_bit, val) {.wr_reg = {\
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#define I_RD_REG(reg, low_bit, high_bit) {.rd_reg = {\
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.addr = reg & 0xff, \
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.addr = (reg & 0xff) / sizeof(uint32_t), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.periph_sel = SOC_REG_TO_ULP_PERIPH_SEL(reg), \
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.unused = 0, \
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.unused = 0, \
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.low = low_bit, \
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.low = low_bit, \
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@ -121,6 +121,45 @@ TEST_CASE("ulp wakeup test", "[ulp][ignore]")
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esp_deep_sleep_start();
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esp_deep_sleep_start();
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}
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}
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TEST_CASE("ulp can write and read peripheral registers", "[ulp]")
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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REG_WRITE(RTC_CNTL_STORE1_REG, 0x89abcdef);
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const ulp_insn_t program[] = {
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I_MOVI(R1, 64),
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I_RD_REG(RTC_CNTL_STORE1_REG, 0, 15),
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I_ST(R0, R1, 0),
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I_RD_REG(RTC_CNTL_STORE1_REG, 4, 11),
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I_ST(R0, R1, 1),
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I_RD_REG(RTC_CNTL_STORE1_REG, 16, 31),
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I_ST(R0, R1, 2),
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I_RD_REG(RTC_CNTL_STORE1_REG, 20, 27),
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I_ST(R0, R1, 3),
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I_WR_REG(RTC_CNTL_STORE0_REG, 0, 7, 0x89),
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I_WR_REG(RTC_CNTL_STORE0_REG, 8, 15, 0xab),
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I_WR_REG(RTC_CNTL_STORE0_REG, 16, 23, 0xcd),
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I_WR_REG(RTC_CNTL_STORE0_REG, 24, 31, 0xef),
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I_LD(R0, R1, 4),
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I_ADDI(R0, R0, 1),
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I_ST(R0, R1, 4),
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I_END(0)
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
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TEST_ESP_OK(ulp_run(0));
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vTaskDelay(100/portTICK_PERIOD_MS);
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TEST_ASSERT_EQUAL_HEX32(0xefcdab89, REG_READ(RTC_CNTL_STORE0_REG));
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TEST_ASSERT_EQUAL_HEX16(0xcdef, RTC_SLOW_MEM[64] & 0xffff);
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TEST_ASSERT_EQUAL_HEX16(0xde, RTC_SLOW_MEM[65] & 0xffff);
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TEST_ASSERT_EQUAL_HEX16(0x89ab, RTC_SLOW_MEM[66] & 0xffff);
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TEST_ASSERT_EQUAL_HEX16(0x9a, RTC_SLOW_MEM[67] & 0xffff);
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TEST_ASSERT_EQUAL_HEX32(1 | (15 << 21) | (1 << 16), RTC_SLOW_MEM[68]);
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}
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TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
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TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
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{
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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