From 04485a655f36ef4bdea6cbdf61556c8dfe116737 Mon Sep 17 00:00:00 2001 From: Lou Tianhao Date: Tue, 16 Jul 2024 21:13:14 +0800 Subject: [PATCH] change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3 squash! change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3 squash! change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3 squash! change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3 --- components/esp_hw_support/port/esp32c5/rtc_clk.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/components/esp_hw_support/port/esp32c5/rtc_clk.c b/components/esp_hw_support/port/esp32c5/rtc_clk.c index 34f4dd7cf5..e3d1052c4b 100644 --- a/components/esp_hw_support/port/esp32c5/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c5/rtc_clk.c @@ -20,6 +20,8 @@ #include "hal/gpio_ll.h" #include "soc/lp_aon_reg.h" #include "esp_private/sleep_event.h" +#include "hal/efuse_hal.h" +#include "soc/chip_revision.h" #if SOC_MODEM_CLOCK_SUPPORTED #include "esp_private/esp_modem_clock.h" @@ -265,9 +267,16 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou divider = 1; } else if (freq_mhz == 80) { real_freq_mhz = freq_mhz; - source = SOC_CPU_CLK_SRC_PLL_F160M; - source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; - divider = 2; + if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) { + // ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M + source = SOC_CPU_CLK_SRC_PLL_F240M; + source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ; + divider = 3; + } else { + source = SOC_CPU_CLK_SRC_PLL_F160M; + source_freq_mhz = CLK_LL_PLL_160M_FREQ_MHZ; + divider = 2; + } } else { // unsupported frequency return false;