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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/can_support_low_bit_rates_backport_v3.2' into 'release/v3.2'
can: Add support for lower bit rates (backport v3.2) See merge request espressif/esp-idf!6390
This commit is contained in:
Angus Gratton
commit
0446bfe1f4
@ -44,12 +44,26 @@
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#define CAN_RESET_FLAG(var, mask) ((var) &= ~(mask))
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#define CAN_TAG "CAN"
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/*
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* Baud Rate Prescaler Divider config/values. The BRP_DIV bit is located in the
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* CAN interrupt enable register, and is only available in ESP32 Revision 2 or
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* later. Setting this bit will cause the APB clock to be prescaled (divided) by
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* a factor 2, before having the BRP applied. This will allow for lower bit rates
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* to be achieved.
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*/
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#define BRP_DIV_EN_THRESH 128 //A BRP config value large this this will need to enable brp_div
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#define BRP_DIV_EN_BIT 0x10 //Bit mask for brp_div in the interrupt register
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//When brp_div is enabled, the BRP config value must be any multiple of 4 between 132 and 256
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#define BRP_CHECK_WITH_DIV(brp) ((brp) >= 132 && (brp) <= 256 && ((brp) & 0x3) == 0)
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//When brp_div is disabled, the BRP config value must be any even number between 2 to 128
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#define BRP_CHECK_NO_DIV(brp) ((brp) >= 2 && (brp) <= 128 && ((brp) & 0x1) == 0)
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//Driver default config/values
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#define DRIVER_DEFAULT_EWL 96 //Default Error Warning Limit value
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#define DRIVER_DEFAULT_TEC 0 //TX Error Counter starting value
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#define DRIVER_DEFAULT_REC 0 //RX Error Counter starting value
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#define DRIVER_DEFAULT_CLKOUT_DIV 14 //APB CLK divided by two
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#define DRIVER_DEFAULT_INTERRUPTS 0xE7 //Exclude data overrun
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#define DRIVER_DEFAULT_INTERRUPTS 0xE7 //Exclude data overrun (bit[3]) and brp_div (bit[4])
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#define DRIVER_DEFAULT_ERR_PASS_CNT 128 //Error counter threshold for error passive
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//Command Bit Masks
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@ -199,7 +213,7 @@ static inline void can_config_bus_timing(uint32_t brp, uint32_t sjw, uint32_t ts
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- SJW (1 to 4) is number of T_scl to shorten/lengthen for bit synchronization
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- TSEG_1 (1 to 16) is number of T_scl in a bit time before sample point
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- TSEG_2 (1 to 8) is number of T_scl in a bit time after sample point
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- triple_sampling will cause each bit time to be sampled 3 times*/
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- triple_sampling will cause each bit time to be sampled 3 times */
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can_bus_tim_0_reg_t timing_reg_0;
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can_bus_tim_1_reg_t timing_reg_1;
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timing_reg_0.baud_rate_prescaler = (brp / 2) - 1;
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@ -629,6 +643,12 @@ esp_err_t can_driver_install(const can_general_config_t *g_config, const can_tim
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CAN_CHECK(g_config->rx_queue_len > 0, ESP_ERR_INVALID_ARG);
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CAN_CHECK(g_config->tx_io >= 0 && g_config->tx_io < GPIO_NUM_MAX, ESP_ERR_INVALID_ARG);
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CAN_CHECK(g_config->rx_io >= 0 && g_config->rx_io < GPIO_NUM_MAX, ESP_ERR_INVALID_ARG);
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#if (CONFIG_ESP32_REV_MIN >= 2)
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//ESP32 revision 2 or later chips have a brp_div bit. Check that the BRP config value is valid when brp_div is enabled or disabled
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CAN_CHECK(BRP_CHECK_WITH_DIV(t_config->brp) || BRP_CHECK_NO_DIV(t_config->brp), ESP_ERR_INVALID_ARG);
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#else
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CAN_CHECK(BRP_CHECK_NO_DIV(t_config->brp), ESP_ERR_INVALID_ARG);
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#endif
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esp_err_t ret;
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can_obj_t *p_can_obj_dummy;
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@ -685,8 +705,14 @@ esp_err_t can_driver_install(const can_general_config_t *g_config, const can_tim
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/* Note: REC is allowed to increase even in reset mode. Listen only mode
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will freeze REC. The desired mode will be set when can_start() is called. */
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can_config_mode(CAN_MODE_LISTEN_ONLY);
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#if (CONFIG_ESP32_REV_MIN >= 2)
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//If the BRP config value is large enough, the brp_div bit must be enabled to achieve the same effective baud rate prescaler
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can_config_interrupts((t_config->brp > BRP_DIV_EN_THRESH) ? DRIVER_DEFAULT_INTERRUPTS | BRP_DIV_EN_BIT : DRIVER_DEFAULT_INTERRUPTS);
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can_config_bus_timing((t_config->brp > BRP_DIV_EN_THRESH) ? t_config->brp/2 : t_config->brp, t_config->sjw, t_config->tseg_1, t_config->tseg_2, t_config->triple_sampling);
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#else
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can_config_interrupts(DRIVER_DEFAULT_INTERRUPTS);
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can_config_bus_timing(t_config->brp, t_config->sjw, t_config->tseg_1, t_config->tseg_2, t_config->triple_sampling);
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#endif
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can_config_error(DRIVER_DEFAULT_EWL, DRIVER_DEFAULT_REC, DRIVER_DEFAULT_TEC);
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can_config_acceptance_filter(f_config->acceptance_code, f_config->acceptance_mask, f_config->single_filter);
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can_config_clk_out(g_config->clkout_divider);
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@ -44,7 +44,13 @@ extern "C" {
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* The following initializer macros offer commonly found bit rates.
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*
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* @note These timing values are based on the assumption APB clock is at 80MHz
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* @note The 20K, 16K and 12.5K bit rates are only available from ESP32 Revision 2 onwards
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*/
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#if (CONFIG_ESP32_REV_MIN >= 2)
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#define CAN_TIMING_CONFIG_12_5KBITS() {.brp = 256, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
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#define CAN_TIMING_CONFIG_16KBITS() {.brp = 200, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
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#define CAN_TIMING_CONFIG_20KBITS() {.brp = 200, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
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#endif
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#define CAN_TIMING_CONFIG_25KBITS() {.brp = 128, .tseg_1 = 16, .tseg_2 = 8, .sjw = 3, .triple_sampling = false}
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#define CAN_TIMING_CONFIG_50KBITS() {.brp = 80, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
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#define CAN_TIMING_CONFIG_100KBITS() {.brp = 40, .tseg_1 = 15, .tseg_2 = 4, .sjw = 3, .triple_sampling = false}
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@ -152,7 +158,8 @@ typedef struct {
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* @note Macro initializers are available for this structure
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*/
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typedef struct {
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uint8_t brp; /**< Baudrate prescaler (APB clock divider, even number from 2 to 128) */
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uint32_t brp; /**< Baudrate prescaler (i.e., APB clock divider) can be any even number from 2 to 128.
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For ESP32 Rev 2 or later, multiples of 4 from 132 to 256 are also supported */
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uint8_t tseg_1; /**< Timing segment 1 (Number of time quanta, between 1 to 16) */
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uint8_t tseg_2; /**< Timing segment 2 (Number of time quanta, 1 to 8) */
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uint8_t sjw; /**< Synchronization Jump Width (Max time quanta jump for synchronize from 1 to 4) */
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@ -91,7 +91,7 @@ typedef union {
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uint32_t tx: 1; /* IER.1 Transmit Interrupt Enable */
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uint32_t err_warn: 1; /* IER.2 Error Interrupt Enable */
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uint32_t data_overrun: 1; /* IER.3 Data Overrun Interrupt Enable */
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uint32_t reserved1: 1; /* Internal Reserved (Wake-up not supported) */
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uint32_t brp_div: 1; /* THIS IS NOT AN INTERRUPT. brp_div will prescale BRP by 2. Only available on ESP32 Revision 2 or later. Reserved otherwise */
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uint32_t err_passive: 1; /* IER.5 Error Passive Interrupt Enable */
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uint32_t arb_lost: 1; /* IER.6 Arbitration Lost Interrupt Enable */
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uint32_t bus_err: 1; /* IER.7 Bus Error Interrupt Enable */
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@ -226,7 +226,9 @@ following segments in the following order:
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The **Baudrate Prescaler** is used to determine the period of each time quanta by
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dividing the CAN controller's source clock (80 MHz APB clock). The ``brp`` can be
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**any even number from 2 to 128**.
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**any even number from 2 to 128**. If the ESP32 is a revision 2 or later chip, the
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``brp`` will also support **any multiple of 4 from 132 to 256**, and can be enabled
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by setting the :ref:`CONFIG_ESP32_REV_MIN` to revision 2 or higher.
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.. packetdiag:: ../../../_static/diagrams/can/can_bit_timing.diag
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:caption: Bit timing configuration for 500kbit/s given BRP = 8
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@ -249,6 +251,9 @@ purposes. ``sjw`` can **range from 1 to 4**.
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Bit timing **macro initializers** are also available for commonly used CAN bus bit rates.
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The following macro initiliazers are provided by the CAN driver.
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- ``CAN_TIMING_CONFIG_12_5KBITS()``
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- ``CAN_TIMING_CONFIG_16KBITS()``
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- ``CAN_TIMING_CONFIG_20KBITS()``
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- ``CAN_TIMING_CONFIG_25KBITS()``
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- ``CAN_TIMING_CONFIG_50KBITS()``
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- ``CAN_TIMING_CONFIG_100KBITS()``
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@ -258,6 +263,10 @@ The following macro initiliazers are provided by the CAN driver.
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- ``CAN_TIMING_CONFIG_800KBITS()``
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- ``CAN_TIMING_CONFIG_1MBITS()``
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.. note::
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The macro initializers for 12.5K, 16K, and 20K bit rates are only available
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for ESP32 revision 2 or later.
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Acceptance Filter
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^^^^^^^^^^^^^^^^^
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