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docs: update description of jtag pins for esp32s3 and esp32c3
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@ -192,27 +192,37 @@ The board can be reset by entering ``mon reset`` or ``mon reset halt`` into GDB.
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.. _jtag-debugging-tip-jtag-pins-reconfigured:
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Do not use JTAG pins for something else
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Can JTAG pins be used for other purposes?
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Operation of JTAG may be disturbed, if some other h/w is connected to JTAG pins besides {IDF_TARGET_NAME} module and JTAG adapter. {IDF_TARGET_NAME} JTAG is using the following pins:
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.. only:: SOC_USB_SERIAL_JTAG_SUPPORTED
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{IDF_TARGET_NAME} contains a USB Serial/JTAG Controller which can be used for debugging. By default, {IDF_TARGET_NAME} JTAG interface is connected to the built-in USB SERIAL/JTAG peripheral. For details, please refer to :doc:`Configure {IDF_TARGET_NAME} built-in JTAG Interface <../jtag-debugging/configure-builtin-jtag>`.
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When you use USB Serial/JTAG Controller for debugging, |jtag-gpio-list| can be used for other purposes.
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However, if you switch the USB JTAG interface to the GPIOs by burning eFuses, |jtag-gpio-list| can be used for JTAG debugging. When they perform this function, they cannot be used for other purposes.
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Operation of JTAG may be disturbed, if some other hardware is connected to JTAG pins besides {IDF_TARGET_NAME} module and JTAG adapter. {IDF_TARGET_NAME} JTAG is using the following pins:
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.. include:: {IDF_TARGET_PATH_NAME}.inc
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:start-after: jtag-pins
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:end-before: ---
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JTAG communication will likely fail, if configuration of JTAG pins is changed by user application. If OpenOCD initializes correctly (detects the two Tensilica cores), but loses sync and spews out a lot of DTR/DIR errors when the program is ran, it is likely that the application reconfigures the JTAG pins to something else, or the user forgot to connect Vtar to a JTAG adapter that needed it.
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JTAG communication will likely fail, if configuration of JTAG pins is changed by a user application. If OpenOCD initializes correctly (detects all the CPU cores in the SOC), but loses sync and spews out a lot of DTR/DIR errors when the program is running, it is likely that the application reconfigures the JTAG pins to something else, or the user forgot to connect Vtar to a JTAG adapter that requires it.
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.. highlight:: none
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.. only:: esp32
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Below is an excerpt from series of errors reported by GDB after the application stepped into the code that reconfigured MTDO pin to be an input::
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.. highlight:: none
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates target still busy!
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an exception!
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an overrun!
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cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates target still busy!
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cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an exception!
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cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an overrun!
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Below is an excerpt from series of errors on the dual-core {IDF_TARGET_NAME} reported by GDB after the application stepped into the code that reconfigured MTDO pin to be an input::
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates target still busy!
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an exception!
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cpu0: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an overrun!
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cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates target still busy!
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cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an exception!
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cpu1: xtensa_resume (line 431): DSR (FFFFFFFF) indicates DIR instruction generated an overrun!
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.. _jtag-debugging-security-features:
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