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rtc_clk: Fix rtc8m calibration failure after cpu/core reset

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1. make sure 8md256 clk is enabled before calibration
2. improve bootloader and application startup 8m, 8md256 enable logic
This commit is contained in:
songruojing 2022-05-27 21:54:34 +08:00
parent c8752cee6a
commit 03477a59db
15 changed files with 65 additions and 19 deletions
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11
components/esp_hw_support/port/esp32/rtc_clk_init.c
View File

@ -125,13 +125,16 @@ void rtc_clk_init(rtc_clk_config_t cfg)
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
// We will not power off RC_FAST in bootloader stage even if it is not being used as any
// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
bool need_rc_fast_en = true;
bool need_rc_fast_d256_en = false;
if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
need_rc_fast_d256_en = true;
}
if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) {
bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256;
rtc_clk_8m_enable(true, need_8md256);
}
rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
rtc_clk_fast_src_set(cfg.fast_clk_src);
rtc_clk_slow_src_set(cfg.slow_clk_src);
}

4
components/esp_hw_support/port/esp32/rtc_time.c
View File

@ -40,7 +40,10 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
/* Prepare calibration */
@ -94,6 +97,7 @@ static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cyc
if (cal_clk == RTC_CAL_8MD256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
if (timeout_us == 0) {
/* timed out waiting for calibration */

10
components/esp_hw_support/port/esp32c2/rtc_clk_init.c
View File

@ -67,10 +67,14 @@ void rtc_clk_init(rtc_clk_config_t cfg)
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) {
bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256;
rtc_clk_8m_enable(true, need_8md256);
// We will not power off RC_FAST in bootloader stage even if it is not being used as any
// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
bool need_rc_fast_en = true;
bool need_rc_fast_d256_en = false;
if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
need_rc_fast_d256_en = true;
}
rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
rtc_clk_fast_src_set(cfg.fast_clk_src);
rtc_clk_slow_src_set(cfg.slow_clk_src);
}

4
components/esp_hw_support/port/esp32c2/rtc_time.c
View File

@ -51,7 +51,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
/* Prepare calibration */
@ -107,6 +110,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_8MD256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
return cal_val;

11
components/esp_hw_support/port/esp32c3/rtc_clk_init.c
View File

@ -67,13 +67,16 @@ void rtc_clk_init(rtc_clk_config_t cfg)
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
// We will not power off RC_FAST in bootloader stage even if it is not being used as any
// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
bool need_rc_fast_en = true;
bool need_rc_fast_d256_en = false;
if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
need_rc_fast_d256_en = true;
}
if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) {
bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256;
rtc_clk_8m_enable(true, need_8md256);
}
rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
rtc_clk_fast_src_set(cfg.fast_clk_src);
rtc_clk_slow_src_set(cfg.slow_clk_src);
}

4
components/esp_hw_support/port/esp32c3/rtc_time.c
View File

@ -55,7 +55,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
/* There may be another calibration process already running during we call this function,
@ -116,6 +119,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_8MD256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
return cal_val;

11
components/esp_hw_support/port/esp32s2/rtc_clk_init.c
View File

@ -67,13 +67,16 @@ void rtc_clk_init(rtc_clk_config_t cfg)
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
// We will not power off RC_FAST in bootloader stage even if it is not being used as any
// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
bool need_rc_fast_en = true;
bool need_rc_fast_d256_en = false;
if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
need_rc_fast_d256_en = true;
}
if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) {
bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256;
rtc_clk_8m_enable(true, need_8md256);
}
rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
rtc_clk_fast_src_set(cfg.fast_clk_src);
rtc_clk_slow_src_set(cfg.slow_clk_src);
}

4
components/esp_hw_support/port/esp32s2/rtc_time.c
View File

@ -157,7 +157,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
@ -177,6 +180,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles, ui
if (cal_clk == RTC_CAL_8MD256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
return cal_val;

11
components/esp_hw_support/port/esp32s3/rtc_clk_init.c
View File

@ -63,13 +63,16 @@ void rtc_clk_init(rtc_clk_config_t cfg)
cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
/* Slow & fast clocks setup */
// We will not power off RC_FAST in bootloader stage even if it is not being used as any
// cpu / rtc_fast / rtc_slow clock sources, this is because RNG always needs it in the bootloader stage.
bool need_rc_fast_en = true;
bool need_rc_fast_d256_en = false;
if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
rtc_clk_32k_enable(true);
} else if (cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
need_rc_fast_d256_en = true;
}
if (cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_RC_FAST) {
bool need_8md256 = cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256;
rtc_clk_8m_enable(true, need_8md256);
}
rtc_clk_8m_enable(need_rc_fast_en, need_rc_fast_d256_en);
rtc_clk_fast_src_set(cfg.fast_clk_src);
rtc_clk_slow_src_set(cfg.slow_clk_src);
}

4
components/esp_hw_support/port/esp32s3/rtc_time.c
View File

@ -53,7 +53,10 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
clk_ll_xtal32k_digi_enable();
}
bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
if (cal_clk == RTC_CAL_8MD256) {
rtc_clk_8m_enable(true, true);
clk_ll_rc_fast_d256_digi_enable();
}
/* There may be another calibration process already running during we call this function,
@ -114,6 +117,7 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
if (cal_clk == RTC_CAL_8MD256) {
clk_ll_rc_fast_d256_digi_disable();
rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
}
return cal_val;

2
components/esp_system/port/soc/esp32/clk.c
View File

@ -131,6 +131,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk)
assert(rtc_clk_xtal_freq_get() != RTC_XTAL_FREQ_AUTO);
#endif
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE

2
components/esp_system/port/soc/esp32c2/clk.c
View File

@ -73,6 +73,8 @@ static const char *TAG = "clk";
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#endif

2
components/esp_system/port/soc/esp32c3/clk.c
View File

@ -75,6 +75,8 @@ static const char *TAG = "clk";
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#endif

2
components/esp_system/port/soc/esp32s2/clk.c
View File

@ -74,6 +74,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
}
rtc_init(cfg);
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE

2
components/esp_system/port/soc/esp32s3/clk.c
View File

@ -72,6 +72,8 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M);
bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled();
rtc_clk_8m_enable(true, rc_fast_d256_is_enabled);
rtc_clk_fast_src_set(SOC_RTC_FAST_CLK_SRC_RC_FAST);
#ifdef CONFIG_BOOTLOADER_WDT_ENABLE