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fix(usb_serial_jtag): Fix issue that use u32_reg read/write cannot be used to modify fifo regs

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This commit is contained in:
C.S.M 2024-07-29 11:46:52 +08:00
parent a0dbe28c9f
commit 03447f5827
3 changed files with 12 additions and 15 deletions
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9
components/soc/esp32c6/include/soc/usb_serial_jtag_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,8 +23,7 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t rdwr_byte:8;
uint32_t reserved_8:24;
uint32_t rdwr_byte:32;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
@ -131,7 +130,7 @@ typedef union {
*/
uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
* USB pad one in test
*/
uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
@ -290,7 +289,7 @@ typedef union {
*/
uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
* CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/
uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;

9
components/soc/esp32h2/include/soc/usb_serial_jtag_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,8 +23,7 @@ typedef union {
* can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know
* how many data is received, then read data from UART Rx FIFO.
*/
uint32_t rdwr_byte:8;
uint32_t reserved_8:24;
uint32_t rdwr_byte:32;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
@ -131,7 +130,7 @@ typedef union {
*/
uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
* USB pad one in test
*/
uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
@ -290,7 +289,7 @@ typedef union {
*/
uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
* CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/
uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;

9
components/soc/esp32p4/include/soc/usb_serial_jtag_struct.h
View File

@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -23,8 +23,7 @@ typedef union {
* USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is
* received, then read data from UART Rx FIFO.
*/
uint32_t rdwr_byte:8;
uint32_t reserved_8:24;
uint32_t rdwr_byte:32;
};
uint32_t val;
} usb_serial_jtag_ep1_reg_t;
@ -131,7 +130,7 @@ typedef union {
*/
uint32_t test_enable:1;
/** test_usb_oe : R/W; bitpos: [1]; default: 0;
* USB pad oen in test
* USB pad one in test
*/
uint32_t test_usb_oe:1;
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
@ -290,7 +289,7 @@ typedef union {
*/
uint32_t serial_out_afifo_reset_rd:1;
/** serial_out_afifo_rempty : RO; bitpos: [4]; default: 1;
* CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
* CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
*/
uint32_t serial_out_afifo_rempty:1;
/** serial_in_afifo_wfull : RO; bitpos: [5]; default: 0;