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Merge branch 'feature/esp32c6_ieee802154_support' into 'master'

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ieee802154: add ieee802154 support for esp32c6

See merge request espressif/esp-idf!21615
This commit is contained in:
Shu Chen 2022-12-22 18:01:58 +08:00
commit 0215575606
15 changed files with 84 additions and 145 deletions
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2
components/bt/controller/esp32c3/bt.c
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@ -38,7 +38,7 @@
#include "esp32c3/rom/rom_layout.h"
#include "esp_timer.h"
#include "esp_sleep.h"
#include "phy.h"
#include "esp_private/phy.h"
#if CONFIG_BT_ENABLED

111
components/efuse/esp32c6/esp_efuse_table.c
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@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c
// md5_digest_table 19131923372be226ce98d85f5a13f16a
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -340,48 +340,9 @@ static const esp_efuse_desc_t MAC_FACTORY[] = {
{EFUSE_BLK1, 0, 8}, // Factory MAC addr [5],
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = {
{EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = {
{EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = {
{EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = {
{EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = {
{EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = {
{EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2),
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = {
{EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = {
{EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = {
{EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = {
{EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6,
};
static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = {
{EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7,
static const esp_efuse_desc_t MAC_EXT[] = {
{EFUSE_BLK1, 48, 8}, // Extend MAC addr [0],
{EFUSE_BLK1, 56, 8}, // Extend MAC addr [1],
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
@ -397,10 +358,6 @@ static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 120, 3}, // BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 184, 2}, // WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID,
};
@ -918,58 +875,9 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = {
&SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = {
&SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = {
&SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = {
&SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = {
&SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = {
&SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = {
&SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = {
&SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = {
&SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = {
&SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = {
&SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7
const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = {
&MAC_EXT[0], // Extend MAC addr [0]
&MAC_EXT[1], // Extend MAC addr [1]
NULL
};
@ -989,11 +897,6 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
&OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID
NULL

26
components/efuse/esp32c6/esp_efuse_table.csv
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@ -104,39 +104,23 @@
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_SYS BLOCK#
# MAC_SYS_VERSION BLOCK #
#######################
# RD_MAC_SPI_SYS_0 - RD_MAC_SPI_SYS_2
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
# RD_MAC_SPI_SYS_3
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
MAC_EXT, EFUSE_BLK1, 48, 8, Extend MAC addr [0]
, EFUSE_BLK1, 56, 8, Extend MAC addr [1]
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 183, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR most significant bit is from RD_MAC_SPI_SYS_5
PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32C3
BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, BLK_VERSION_MINOR
# RD_MAC_SPI_SYS_5
# WAFER_VERSION_MINOR most significant bit
WAFER_VERSION_MAJOR, EFUSE_BLK1, 184, 2, WAFER_VERSION_MAJOR
# SYS_DATA_PART1 BLOCK# - System configuration
# SYS_DATA_PART1 BLOCK# - System configuration (TODO: IDF-6483) #
#######################
# RD_SYS_PART1_DATA0 - rd_sys_part1_data3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
@ -169,7 +153,7 @@ KEY4, EFUSE_BLK8, 0, 256, Key4 or us
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
# AUTO CONFIG DIG&RTC DBIAS#
# AUTO CONFIG DIG&RTC DBIAS (TODO: IDF-6483)#
################
K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO
K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO

Can't render this file because it contains an unexpected character in line 7 and column 87.

15
components/efuse/esp32c6/include/esp_efuse_table.h
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@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table e3b1264d26cc94f387d58e4ba9a3677c
// md5_digest_table 19131923372be226ce98d85f5a13f16a
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@ -97,21 +97,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];

4
components/esp_phy/CMakeLists.txt
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@ -21,6 +21,10 @@ else()
list(APPEND srcs "src/phy_init.c")
endif()
if(CONFIG_SOC_BT_SUPPORTED OR CONFIG_SOC_IEEE802154_SUPPORTED)
list(APPEND srcs "src/btbb_init.c")
endif()
idf_build_get_property(build_dir BUILD_DIR)
if(CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN)

10
components/esp_phy/include/esp_phy_init.h
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@ -170,6 +170,16 @@ void esp_phy_enable(void);
*/
void esp_phy_disable(void);
/**
* @brief Enable BTBB module
*
* BTBB module should be enabled in order to use IEEE802154 or BT.
* Now BTBB enabling job is done automatically when start IEEE802154 or BT. Users should not
* call this API in their application.
*
*/
void esp_btbb_enable(void);
/**
* @brief Load calibration data from NVS and initialize PHY and RF module
*/

23
components/esp_phy/include/esp_private/btbb.h Normal file
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@ -0,0 +1,23 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set btbb enable for BT/ieee802154
* @param[in] print_version enable btbb version print.
* @return NULL
*/
void bt_bb_v2_init_cmplx(int print_version);
#ifdef __cplusplus
}
#endif

0
components/esp_phy/include/phy.h → components/esp_phy/include/esp_private/phy.h
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25
components/esp_phy/src/btbb_init.c Normal file
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@ -0,0 +1,25 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include "freertos/FreeRTOS.h"
#include "esp_private/btbb.h"
#define BTBB_ENABLE_VERSION_PRINT 1
static _lock_t s_btbb_access_lock;
/* Reference count of enabling BT BB */
static uint8_t s_btbb_access_ref = 0;
void esp_btbb_enable(void)
{
_lock_acquire(&s_btbb_access_lock);
if (s_btbb_access_ref == 0) {
bt_bb_v2_init_cmplx(BTBB_ENABLE_VERSION_PRINT);
}
s_btbb_access_ref++;
_lock_release(&s_btbb_access_lock);
}

2
components/esp_phy/src/phy_init.c
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@ -23,7 +23,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/portmacro.h"
#include "endian.h"
#include "phy.h"
#include "esp_private/phy.h"
#include "phy_init_data.h"
#include "esp_coexist_internal.h"
#include "esp_private/periph_ctrl.h"

2
components/esp_phy/src/phy_init_esp32hxx.c
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@ -7,7 +7,7 @@
#include "esp_attr.h"
#include "freertos/portmacro.h"
#include "esp_phy_init.h"
#include "phy.h"
#include "esp_private/phy.h"
#define PHY_ENABLE_VERSION_PRINT 1

2
components/esp_wifi/src/wifi_init.c
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@ -17,7 +17,7 @@
#include "esp_netif.h"
#include "esp_coexist_internal.h"
#include "esp_phy_init.h"
#include "phy.h"
#include "esp_private/phy.h"
#if (CONFIG_ESP32_WIFI_RX_BA_WIN > CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM)
#error "WiFi configuration check: WARNING, WIFI_RX_BA_WIN should not be larger than WIFI_DYNAMIC_RX_BUFFER_NUM!"

4
components/ieee802154/Kconfig
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@ -1,8 +1,8 @@
menu "IEEE 802.15.4"
visible if IDF_TARGET_ESP32H4
visible if SOC_IEEE802154_SUPPORTED
config IEEE802154_ENABLED
bool
default "y" if IDF_TARGET_ESP32H4
default "y" if SOC_IEEE802154_SUPPORTED
endmenu # IEEE 802.15.4

2
components/ieee802154/lib

@ -1 +1 @@
Subproject commit 5c51d657d4d34f60890540587663925462ababa4
Subproject commit 7c691d705b491c1dbb53fa6a15e23b1c4ccb287f

1
components/soc/esp32c6/ld/esp32c6.peripherals.ld
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@ -74,3 +74,4 @@ PROVIDE ( LPPERI = 0x600B2800 );
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
PROVIDE ( LP_APM = 0x600B3800 );
PROVIDE ( OTP_DEBUG = 0x600B3C00 );
PROVIDE ( IEEE802154 = 0x600A3000 );