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refactor(sar): build sar_periph_ctrl related files by chip
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5bd644942a
commit
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@ -37,11 +37,11 @@ entries:
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mspi_timing_config (noflash)
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if SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY = y:
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mspi_timing_by_mspi_delay (noflash)
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if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
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sar_periph_ctrl (noflash)
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else:
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sar_periph_ctrl: sar_periph_ctrl_power_enable (noflash)
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if SOC_ADC_SHARED_POWER = y:
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if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
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sar_periph_ctrl (noflash)
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else:
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sar_periph_ctrl: sar_periph_ctrl_power_enable (noflash)
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[mapping:soc_pm]
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archive: libsoc.a
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@ -235,6 +235,10 @@ config SOC_ADC_RTC_MAX_BITWIDTH
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int
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default 12
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config SOC_ADC_SHARED_POWER
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bool
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default y
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config SOC_SHARED_IDCACHE_SUPPORTED
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bool
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default y
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@ -134,6 +134,9 @@
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#define SOC_ADC_RTC_MIN_BITWIDTH (9)
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#define SOC_ADC_RTC_MAX_BITWIDTH (12)
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/*!< ADC power control is shared by PWDET */
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#define SOC_ADC_SHARED_POWER 1
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#if SOC_CAPS_ECO_VER >= 100
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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@ -179,6 +179,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
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bool
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default y
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config SOC_ADC_SHARED_POWER
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bool
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default y
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config SOC_BROWNOUT_RESET_SUPPORTED
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bool
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default y
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@ -84,6 +84,9 @@
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#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
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#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
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/*!< ADC power control is shared by PWDET, TempSensor */
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#define SOC_ADC_SHARED_POWER 1
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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@ -259,6 +259,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
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bool
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default y
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config SOC_ADC_SHARED_POWER
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bool
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default y
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config SOC_APB_BACKUP_DMA
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bool
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default y
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@ -112,6 +112,9 @@
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#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
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#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
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/*!< ADC power control is shared by PWDET, TempSensor */
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#define SOC_ADC_SHARED_POWER 1
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (1)
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@ -315,6 +315,10 @@ config SOC_ADC_TEMPERATURE_SHARE_INTR
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bool
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default y
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config SOC_ADC_SHARED_POWER
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bool
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default y
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config SOC_APB_BACKUP_DMA
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bool
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default n
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@ -125,6 +125,9 @@
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/*!< Interrupt */
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#define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
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/*!< ADC power control is shared by PWDET */
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#define SOC_ADC_SHARED_POWER 1
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// ESP32C6-TODO: Copy from esp32c6, need check
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (0)
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@ -295,6 +295,10 @@ config SOC_ADC_TEMPERATURE_SHARE_INTR
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bool
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default y
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config SOC_ADC_SHARED_POWER
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bool
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default y
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config SOC_APB_BACKUP_DMA
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bool
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default n
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@ -121,6 +121,9 @@
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/*!< Interrupt */
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#define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
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/*!< ADC power control is shared by PWDET */
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#define SOC_ADC_SHARED_POWER 1
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// ESP32H2-TODO: Copy from esp32c6, need check
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (0)
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@ -275,6 +275,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
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bool
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default y
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config SOC_ADC_SHARED_POWER
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bool
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default y
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config SOC_BROWNOUT_RESET_SUPPORTED
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bool
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default y
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@ -122,6 +122,9 @@
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#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
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#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
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/*!< ADC power control is shared by PWDET, TempSensor */
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#define SOC_ADC_SHARED_POWER 1
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/*-------------------------- BROWNOUT CAPS -----------------------------------*/
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#define SOC_BROWNOUT_RESET_SUPPORTED 1
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@ -315,6 +315,10 @@ config SOC_ADC_SELF_HW_CALI_SUPPORTED
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bool
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default y
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config SOC_ADC_SHARED_POWER
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bool
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default y
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config SOC_APB_BACKUP_DMA
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bool
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default y
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@ -115,6 +115,9 @@
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#define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
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#define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */
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/*!< ADC power control is shared by PWDET, TempSensor */
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#define SOC_ADC_SHARED_POWER 1
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/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/
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#define SOC_APB_BACKUP_DMA (1)
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