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Merge branch 'fix/esp32c5_interrupt_support' into 'master'

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fix(esp32c5): add CLIC interrupt controller support for the ESP32-C5 (Beta3 & MP)

Closes IDF-8654 and IDF-8655

See merge request espressif/esp-idf!30017
This commit is contained in:
Omar Chebib 2024-04-16 16:35:49 +08:00
commit 007a626049
15 changed files with 658 additions and 629 deletions
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31
components/freertos/FreeRTOS-Kernel/portable/riscv/include/freertos/portmacro.h
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@ -146,7 +146,7 @@ typedef uint32_t TickType_t;
UBaseType_t xPortSetInterruptMaskFromISR(void);
/**
* @brief Reenable interrupts in a nested manner (meant to be called from ISRs)
* @brief Re-enable interrupts in a nested manner (meant to be called from ISRs)
*
* @warning Only applies to current CPU.
* @param prev_int_level Previous interrupt level
@ -663,27 +663,10 @@ static inline void __attribute__((always_inline)) vPortExitCriticalSafe(portMUX_
// ---------------------- Yielding -------------------------
// TODO: [ESP32C61] IDF-9280, changed in verify code, pls check
#if CONFIG_IDF_TARGET_ESP32C61
FORCE_INLINE_ATTR bool xPortCanYield(void)
{
#if SOC_INT_CLIC_SUPPORTED
uint32_t threshold1 = (RV_READ_CSR(MINTTHRESH)) >> (8 - NLBITS);
uint32_t threshold2 = (RV_READ_CSR(MINTSTATUS)) >> (24 + (8 - NLBITS));
return (threshold1 == 0) && (threshold2 == 0) ;
#else
uint32_t threshold = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
return (threshold <= 1);
#endif /* SOC_INT_CLIC_SUPPORTED */
}
#else
FORCE_INLINE_ATTR bool xPortCanYield(void)
{
#if SOC_INT_CLIC_SUPPORTED
// TODO: [ESP32C5] IDF-8655 simplify the code for c5 mp
#if !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
uint32_t threshold = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
/* When CLIC is supported:
* - The lowest interrupt threshold level is 0. Therefore, an interrupt threshold level above 0 would mean that we
* are in a critical section.
@ -692,18 +675,9 @@ FORCE_INLINE_ATTR bool xPortCanYield(void)
* level, we read the machine-mode interrupt level (mil) field from the mintstatus CSR. A non-zero value indicates
* that we are in an interrupt context.
*/
uint32_t threshold = rv_utils_get_interrupt_threshold();
uint32_t intr_level = rv_utils_get_interrupt_level();
threshold = threshold >> (CLIC_CPU_INT_THRESH_S + (8 - NLBITS));
return ((intr_level == 0) && (threshold == 0));
#else
#define MINTSTATUS 0xfb1
#define MINTTHRESH 0x347
uint32_t threshold1 = (RV_READ_CSR(MINTTHRESH)) >> (8 - NLBITS);
uint32_t threshold2 = (RV_READ_CSR(MINTSTATUS)) >> (24 + (8 - NLBITS));
return (threshold1 == 0) && (threshold2 == 0) ;
#endif
#else/* !SOC_INT_CLIC_SUPPORTED */
uint32_t threshold = REG_READ(INTERRUPT_CURRENT_CORE_INT_THRESH_REG);
/* when enter critical code, FreeRTOS will mask threshold to RVHAL_EXCM_LEVEL
@ -713,7 +687,6 @@ FORCE_INLINE_ATTR bool xPortCanYield(void)
return (threshold <= 1);
#endif
}
#endif
/* ------------------------------------------------------ Misc ---------------------------------------------------------
* - Miscellaneous porting macros

2
components/hal/include/hal/interrupt_intc_ll.h
View File

@ -8,7 +8,7 @@
#include "soc/soc_caps.h"
#include "soc/reg_base.h"
/* Do not use INTC on targets that have harware CLIC */
/* Do not use INTC on targets that have hardware CLIC */
#if SOC_CPU_HAS_FLEXIBLE_INTC && !SOC_INT_CLIC_SUPPORTED
#include "soc/interrupt_reg.h"

218
components/riscv/include/esp_private/interrupt_clic.h
View File

@ -5,16 +5,33 @@
*/
#pragma once
#include "sdkconfig.h"
#include <stdint.h>
#include <assert.h>
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "esp_attr.h"
#include "riscv/csr.h"
#if SOC_INT_CLIC_SUPPORTED
#include "soc/clic_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set global masking level. When using the CLIC, all interrupt priority levels less than or equal to the threshold
* level are masked. Since the default priority for the interrupt is 1, set this macro to 0 to enable them all.
*/
#define RVHAL_INTR_ENABLE_THRESH 0
/**
* @brief Bitmask to enable the vector mode when writing MTVEC CSR.
* Setting mode field to 3 treats `MTVT + 4 * interrupt_id` as the service entry address for HW vectored interrupts.
*/
#define MTVEC_MODE_CSR 3
/**
* If the target is using the CLIC as the interrupt controller, we have 32 external interrupt lines and 16 internal
@ -23,13 +40,212 @@ extern "C" {
#define RV_EXTERNAL_INT_COUNT 32
#define RV_EXTERNAL_INT_OFFSET 16
/**
* @brief CSR to set the interrupt jump table address is MTVT.
*/
#define MTVT_CSR 0x307
/**
* @brief Convert a priority level from 8-bit to NLBITS and NLBITS to 8-bit
*
* On CLIC, the interrupt threshold is stored in the upper (NLBITS) of the mintthresh register, with the other (8 - NLBITS)
* defaulted to 1. We form the interrupt level bits here to avoid doing this at run time
*/
#define NLBITS_SHIFT (8 - NLBITS)
#define NLBITS_MASK ((1 << NLBITS) - 1)
#define BYTE_TO_NLBITS(level) (((level) >> NLBITS_SHIFT) & NLBITS_MASK)
/* Align the level to the left, and put 1 in the lowest bits */
#define NLBITS_TO_BYTE(level) (((level) << NLBITS_SHIFT) | ((1 << NLBITS_SHIFT) - 1))
/* Helper macro to translate absolute interrupt level to CLIC interrupt threshold bits in the mintthresh reg */
#define CLIC_INT_THRESH(intlevel) (NLBITS_TO_BYTE(intlevel) << CLIC_CPU_INT_THRESH_S)
/* Helper macro to translate a CLIC interrupt threshold bits to an absolute interrupt level */
#define CLIC_THRESH_TO_INT(intlevel) (BYTE_TO_NLBITS((intlevel >> CLIC_CPU_INT_THRESH_S) & CLIC_CPU_INT_THRESH_V))
/* Helper macro to set interrupt level RVHAL_EXCM_LEVEL. Used during critical sections */
#define RVHAL_EXCM_LEVEL_CLIC (CLIC_INT_THRESH(RVHAL_EXCM_LEVEL - 1))
/* Helper macro to enable interrupts. */
#define RVHAL_INTR_ENABLE_THRESH_CLIC (CLIC_INT_THRESH(RVHAL_INTR_ENABLE_THRESH))
#if CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
/**
* The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
* - The interrupt threshold is configured via a memory-mapped register instead of a CSR
* - The mintstatus CSR is at 0x346 instead of 0xFB1 as per the official specification
*/
#define INTTHRESH_STANDARD 0
#define MINTSTATUS_CSR 0x346
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
/* The ESP32-C5 (MP) and C61 use the standard CLIC specification, for example, it defines the mintthresh CSR */
#define INTTHRESH_STANDARD 1
#define MINTSTATUS_CSR 0xFB1
#define MINTTHRESH_CSR 0x347
#else
#error "Check the implementation of the CLIC on this target."
#endif
FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
{
assert(rv_int_num < RV_EXTERNAL_INT_COUNT && "Invalid CPU interrupt number");
}
/* -------------------------------------------------------------------------- */
/* Interrupt Configuration part of rv_utils */
/* -------------------------------------------------------------------------- */
/**
* @brief Get the current CPU threshold level
*/
FORCE_INLINE_ATTR uint32_t rv_utils_get_interrupt_threshold(void)
{
#if INTTHRESH_STANDARD
uint32_t threshold = RV_READ_CSR(MINTTHRESH_CSR);
#else
uint32_t threshold = REG_READ(CLIC_INT_THRESH_REG);
#endif
return CLIC_THRESH_TO_INT(threshold);
}
/**
* @brief Set the MTVT CSR value, used as a base address for the interrupt jump table
*/
FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val)
{
RV_WRITE_CSR(MTVT_CSR, mtvt_val);
}
/**
* @brief Get the current CPU raw interrupt level
*/
FORCE_INLINE_ATTR uint32_t rv_utils_get_interrupt_level_regval(void)
{
return RV_READ_CSR(MINTSTATUS_CSR);
}
/**
* @brief Get the current CPU interrupt level, between 0 and 2^NLBITS - 1
*/
FORCE_INLINE_ATTR uint32_t rv_utils_get_interrupt_level(void)
{
const uint32_t mintstatus = RV_READ_CSR(MINTSTATUS_CSR);
/* Extract the level from this field */
return CLIC_THRESH_TO_INT(mintstatus);
}
/**
* @brief Restore the CPU interrupt level to the value returned by `rv_utils_set_intlevel_regval`.
*
* @note This function doesn't process its parameter, it is therefore faster than its counterpart, `rv_utils_restore_intlevel`, and should be used in places where speed is important (spinlocks, critical sections, ...)
*
* @param restoreval Former raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
*/
FORCE_INLINE_ATTR void rv_utils_restore_intlevel_regval(uint32_t restoreval)
{
#if INTTHRESH_STANDARD
RV_WRITE_CSR(MINTTHRESH_CSR, restoreval);
#else
REG_WRITE(CLIC_INT_THRESH_REG, restoreval);
/**
* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
* operations is forced, making the new threshold active. It is then safe to re-enable MIE bit in mstatus.
*/
REG_READ(CLIC_INT_THRESH_REG);
#endif
}
/**
* @brief Restore the CPU interrupt level to the given priority.
*
* @note On the CLIC, the interrupt level mask is inclusive, so this function would mask all interrupts between 0 and `restoreval`.
*/
FORCE_INLINE_ATTR void rv_utils_restore_intlevel(uint32_t restoreval)
{
rv_utils_restore_intlevel_regval(CLIC_INT_THRESH(restoreval));
}
/**
* @brief Set the interrupt threshold to `intlevel` while getting the current level.
*
* @note This function doesn't process its parameter nor the returned value, it is therefore faster than its counterpart, `rv_utils_set_intlevel`, and should be used in places where speed is important (spinlocks, critical sections, ...)
*
* @param intlevel New raw interrupt level, it is NOT necessarily a value between 0 and 7, this is hardware and configuration dependent.
*
* @return Current raw interrupt level, can be restored by calling `rv_utils_restore_intlevel_regval`.
*/
FORCE_INLINE_ATTR uint32_t rv_utils_set_intlevel_regval(uint32_t intlevel)
{
#if INTTHRESH_STANDARD
return RV_SWAP_CSR(MINTTHRESH_CSR, intlevel);
#else // !INTTHRESH_STANDARD
uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
uint32_t old_thresh = REG_READ(CLIC_INT_THRESH_REG);
/* This function expects the interrupt level to be available in the format needed for mintthresh reg.
* Providing an absolute interrupt level will result in incorrect behavior.
* See CLIC_INT_THRESH() macro for details of how the interrupt level must be provided. */
rv_utils_restore_intlevel_regval(intlevel);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
/* We return the mintthresh register value and NOT the absolute interrupt threshold level.
* This is done to avoid extra bit manipulations during critical sections. */
return old_thresh;
#endif // INTTHRESH_STANDARD
}
FORCE_INLINE_ATTR uint32_t rv_utils_set_intlevel(uint32_t intlevel)
{
const uint32_t former = rv_utils_set_intlevel_regval(CLIC_INT_THRESH(intlevel));
return CLIC_THRESH_TO_INT(former);
}
FORCE_INLINE_ATTR uint32_t rv_utils_mask_int_level_lower_than(uint32_t intlevel)
{
/* CLIC's set interrupt level is inclusive, i.e. it DOES mask the level set.
* For example, if we want to mask interrupt level lower than 3, we have to set the intlevel to 2. */
return rv_utils_set_intlevel(intlevel - 1);
}
/**
* @brief Get the enabled interrupts on the current CPU.
*
* @return Bit mask of the enabled interrupts
*/
FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
{
unsigned intr_ena_mask = 0;
unsigned intr_num;
for (intr_num = 0; intr_num < 32; intr_num++) {
if (REG_GET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_IE))
intr_ena_mask |= BIT(intr_num);
}
return intr_ena_mask;
}
/**
* @brief Acknowledge an edge interrupt
*
* @param intr_num Interrupt number (from 0 to 31)
*/
FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(uint32_t intr_num)
{
REG_SET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET) , CLIC_INT_IP);
}
#ifdef __cplusplus
}
#endif
#endif /* SOC_INT_CLIC_SUPPORTED */

38
components/riscv/include/esp_private/interrupt_intc.h
View File

@ -9,12 +9,28 @@
#include <stdint.h>
#include <assert.h>
#include "esp_attr.h"
#include "soc/interrupt_reg.h"
#include "soc/soc_caps.h"
#if !SOC_INT_CLIC_SUPPORTED && !SOC_INT_PLIC_SUPPORTED
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set global masking level. On the legacy INTC, all interrupt priority levels strictly less than the threshold
* level are masked.
*/
#define RVHAL_INTR_ENABLE_THRESH 1
/**
* @brief Bitmask to enable the vector mode when writing MTVEC CSR.
* Setting mode field to 1 treats `MTVEC` as a vector base address.
*/
#define MTVEC_MODE_CSR 1
/**
* In the case of INTC, all the interrupt lines are dedicated to external peripherals, so the offset is 0
*/
@ -27,7 +43,29 @@ FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
assert(rv_int_num != 0 && "Invalid CPU interrupt number");
}
/**
* @brief Get the enabled interrupts on the current CPU.
*
* @return Bit mask of the enabled interrupts
*/
FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
{
return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
}
/**
* @brief Acknowledge an edge interrupt
*
* @param intr_num Interrupt number (from 0 to 31)
*/
FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(uint32_t intr_num)
{
REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
}
#ifdef __cplusplus
}
#endif
#endif /* !SOC_INT_CLIC_SUPPORTED && !SOC_INT_PLIC_SUPPORTED */

39
components/riscv/include/esp_private/interrupt_plic.h
View File

@ -9,12 +9,29 @@
#include <stdint.h>
#include <assert.h>
#include "esp_attr.h"
#include "soc/interrupt_reg.h"
#include "soc/soc_caps.h"
#if SOC_INT_PLIC_SUPPORTED
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set global masking level. On the PLIC, all interrupt priority levels strictly less than the threshold
* level are masked.
*/
#define RVHAL_INTR_ENABLE_THRESH 1
/**
* @brief Bitmask to enable the vector mode when writing MTVEC CSR.
* Setting mode field to 1 treats `MTVEC` as a vector base address.
*/
#define MTVEC_MODE_CSR 1
/**
* In the case of PLIC, all the interrupt lines are dedicated to external peripherals, so the offset is 0
*/
@ -27,7 +44,29 @@ FORCE_INLINE_ATTR void assert_valid_rv_int_num(int rv_int_num)
assert(rv_int_num != 0 && "Invalid CPU interrupt number");
}
/**
* @brief Get the enabled interrupts on the current CPU.
*
* @return Bit mask of the enabled interrupts
*/
FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
{
return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
}
/**
* @brief Acknowledge an edge interrupt
*
* @param intr_num Interrupt number (from 0 to 31)
*/
FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(uint32_t intr_num)
{
REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
}
#ifdef __cplusplus
}
#endif
#endif /* SOC_INT_PLIC_SUPPORTED */

2
components/riscv/include/riscv/interrupt.h
View File

@ -23,7 +23,7 @@ enum intr_type {
#include "esp_private/interrupt_clic.h"
#elif SOC_INT_PLIC_SUPPORTED
#include "esp_private/interrupt_plic.h"
#else
#elif SOC_CPU_HAS_FLEXIBLE_INTC
#include "esp_private/interrupt_intc.h"
#endif

183
components/riscv/include/riscv/rv_utils.h
View File

@ -45,27 +45,6 @@ extern "C" {
and spinlocks */
#define RVHAL_EXCM_LEVEL 4
/* SW defined interrupt threshold level to allow all interrupts */
#if SOC_INT_CLIC_SUPPORTED
/* set global CLIC masking level. When CLIC is supported, all interrupt priority levels less than or equal to the threshold level are masked. */
#define RVHAL_INTR_ENABLE_THRESH 0
#else
#define RVHAL_INTR_ENABLE_THRESH 1
#endif /* SOC_INT_CLIC_SUPPORTED */
/* On CLIC, the interrupt threshold is stored in the upper (NLBITS) of the mintthresh register, with the other (8 - NLBITS)
* defaulted to 1. We form the interrupt level bits here to avoid doing this at run time */
#if SOC_INT_CLIC_SUPPORTED
/* Helper macro to translate absolute interrupt level to CLIC interrupt threshold bits in the mintthresh reg */
#define CLIC_INT_THRESH(intlevel) (((((intlevel) << (8 - NLBITS))) | 0x1f) << CLIC_CPU_INT_THRESH_S)
/* Helper macro to set interrupt level RVHAL_EXCM_LEVEL. Used during critical sections */
#define RVHAL_EXCM_LEVEL_CLIC (CLIC_INT_THRESH(RVHAL_EXCM_LEVEL - 1))
/* Helper macro to enable interrupts. */
#define RVHAL_INTR_ENABLE_THRESH_CLIC (CLIC_INT_THRESH(RVHAL_INTR_ENABLE_THRESH))
#endif /* SOC_INT_CLIC_SUPPORTED */
/* --------------------------------------------------- CPU Control -----------------------------------------------------
*
* ------------------------------------------------------------------------------------------------------------------ */
@ -119,49 +98,13 @@ FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_set_cycle_count(u
*
* ------------------------------------------------------------------------------------------------------------------ */
// ---------------- Interrupt Descriptors ------------------
// --------------- Interrupt Configuration -----------------
#if SOC_INT_CLIC_SUPPORTED
FORCE_INLINE_ATTR void rv_utils_set_mtvt(uint32_t mtvt_val)
{
#define MTVT 0x307
RV_WRITE_CSR(MTVT, mtvt_val);
}
#endif
FORCE_INLINE_ATTR void rv_utils_set_mtvec(uint32_t mtvec_val)
{
#if SOC_INT_CLIC_SUPPORTED
mtvec_val |= 3; // Set MODE field to 3 to treat MTVT + 4*interrupt_id as the service entry address for HW vectored interrupts
#else
mtvec_val |= 1; // Set MODE field to treat MTVEC as a vector base address
#endif
RV_WRITE_CSR(mtvec, mtvec_val);
RV_WRITE_CSR(mtvec, mtvec_val | MTVEC_MODE_CSR);
}
// TODO: [ESP32C5] IDF-8655 need refactor for C5 MP
#if SOC_INT_CLIC_SUPPORTED && !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
FORCE_INLINE_ATTR __attribute__((pure)) uint32_t rv_utils_get_interrupt_level(void)
{
#if CONFIG_IDF_TARGET_ESP32P4
// As per CLIC specs, mintstatus CSR should be at 0xFB1, however esp32p4 implements it at 0x346
#define MINTSTATUS 0x346
#elif CONFIG_IDF_TARGET_ESP32C5
// TODO: [ESP32C5] IDF-8654, IDF-8655 (inherit from P4) Check the correctness
#define MINTSTATUS 0x346
#elif CONFIG_IDF_TARGET_ESP32C61
// TODO: [ESP32C61] IDF-9261, IDF-9262 (inherit from c6) Check
#define MINTSTATUS 0xFB1
#define MINTTHRESH 0x347
#else
#error "rv_utils_get_mintstatus() is not implemented. Check for correct mintstatus register address."
#endif /* CONFIG_IDF_TARGET_ESP32P4 */
uint32_t mintstatus = RV_READ_CSR(MINTSTATUS);
return ((mintstatus >> 24) & 0xFF); // Return the mintstatus[31:24] bits to get the mil field
}
#endif /* SOC_INT_CLIC_SUPPORTED */
// ------------------ Interrupt Control --------------------
FORCE_INLINE_ATTR void rv_utils_intr_enable(uint32_t intr_mask)
@ -180,126 +123,6 @@ FORCE_INLINE_ATTR void rv_utils_intr_disable(uint32_t intr_mask)
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
}
#if SOC_INT_CLIC_SUPPORTED
FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_restore_intlevel(uint32_t restoreval)
{
// TODO: [ESP32C5] IDF-8655 need refactor for C5 MP
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
#define MINTTHRESH 0x347
RV_WRITE_CSR(MINTTHRESH, restoreval);
#elif CONFIG_IDF_TARGET_ESP32C61
// TODO: [ESP32C61] IDF-9261, changed in verify code, pls check
// RV_WRITE_CSR(MINTTHRESH, restoreval);
#else
REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((restoreval << (8 - NLBITS))) | 0x1f);
#endif // !CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
}
FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel(uint32_t intlevel)
{
uint32_t old_thresh;
// TODO: [ESP32C5] IDF-8655 need refactor for C5 MP
#if CONFIG_IDF_TARGET_ESP32C5_MP_VERSION
old_thresh = RV_READ_CSR(MINTTHRESH);
RV_WRITE_CSR(MINTTHRESH, ((intlevel << (8 - NLBITS)) | 0x1f));
#else
// TODO: [ESP32C61] IDF-9261 pls check
uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
old_thresh = REG_GET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH);
old_thresh = (old_thresh >> (8 - NLBITS));
/* Upper bits should already be 0, but let's be safe and keep NLBITS */
old_thresh &= BIT(NLBITS) - 1;
REG_SET_FIELD(CLIC_INT_THRESH_REG, CLIC_CPU_INT_THRESH, ((intlevel << (8 - NLBITS))) | 0x1f);
/**
* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
* operations is forced, making the new threshold active. It is then safe to re-enable MIE bit in mstatus.
*/
REG_READ(CLIC_INT_THRESH_REG);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
#endif
return old_thresh;
}
/* Direct register write version of rv_utils_restore_intlevel(). Used to speed up critical sections. */
FORCE_INLINE_ATTR void __attribute__((always_inline)) rv_utils_restore_intlevel_regval(uint32_t restoreval)
{
/* This function expects restoreval to be in the format needed to restore the interrupt level with
* a single write to the mintthresh register without further manipulations needed.
* This is done to quicken up exit for critical sections */
REG_WRITE(CLIC_INT_THRESH_REG, restoreval);
/**
* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
* operations is forced, making the new threshold active.
*
* Without this we risk executing the next several instructions before getting interrupted
* This is especially bad if we immediately enter a new critical section
*/
REG_READ(CLIC_INT_THRESH_REG);
}
/* Direct register write version of rv_utils_set_intlevel(). Used to speed up critical sections. */
FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_set_intlevel_regval(uint32_t intlevel)
{
uint32_t old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
uint32_t old_thresh = REG_READ(CLIC_INT_THRESH_REG);
/* This function expects the interrupt level to be available in the format needed for mintthresh reg.
* Providing an absolute interrupt level will result in incorrect behavior.
* See CLIC_INT_THRESH() macro for details of how the interrupt level must be provided. */
REG_WRITE(CLIC_INT_THRESH_REG, intlevel);
/**
* After writing the threshold register, the new threshold is not directly taken into account by the CPU.
* By executing ~8 nop instructions, or by performing a memory load right now, the previous memory write
* operations is forced, making the new threshold active. It is then safe to re-enable MIE bit in mstatus.
*/
REG_READ(CLIC_INT_THRESH_REG);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
/* We return the mintthresh register value and NOT the absolute interrupt threshold level.
* This is done to avoid extra bit manipulations during critical sections. */
return old_thresh;
}
FORCE_INLINE_ATTR uint32_t __attribute__((always_inline)) rv_utils_mask_int_level_lower_than(uint32_t intlevel)
{
/* CLIC's set interrupt level is inclusive, i.e. it does mask the set level */
return rv_utils_set_intlevel(intlevel - 1);
}
#endif /* SOC_INT_CLIC_SUPPORTED */
FORCE_INLINE_ATTR uint32_t rv_utils_intr_get_enabled_mask(void)
{
#if SOC_INT_CLIC_SUPPORTED
unsigned intr_ena_mask = 0;
unsigned intr_num;
for (intr_num = 0; intr_num < 32; intr_num++) {
if (REG_GET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET), CLIC_INT_IE))
intr_ena_mask |= BIT(intr_num);
}
return intr_ena_mask;
#else
return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
#endif
}
FORCE_INLINE_ATTR void rv_utils_intr_edge_ack(unsigned int intr_num)
{
#if SOC_INT_CLIC_SUPPORTED
REG_SET_BIT(CLIC_INT_CTRL_REG(intr_num + CLIC_EXT_INTR_NUM_OFFSET) , CLIC_INT_IP);
#else
REG_SET_BIT(INTERRUPT_CORE0_CPU_INT_CLEAR_REG, intr_num);
#endif
}
FORCE_INLINE_ATTR void rv_utils_intr_global_enable(void)
{
RV_SET_CSR(mstatus, MSTATUS_MIE);
@ -310,6 +133,10 @@ FORCE_INLINE_ATTR void rv_utils_intr_global_disable(void)
RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
}
/**
* The other rv_utils functions related to each interrupt controller are defined in `interrupt_clic.h`, `interrupt_plic.h`,
* and `interrupt_intc.h`.
*/
#if SOC_CPU_HAS_FPU

281
components/soc/esp32c5/beta3/include/soc/interrupt_matrix_reg.h
View File

@ -1,12 +1,11 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc.h"
#ifdef __cplusplus
extern "C" {
#endif
@ -395,34 +394,22 @@ extern "C" {
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG register
* GPIO_INTERRUPT_PRO_NMI mapping register
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG register
* GPIO_INTERRUPT_EXT mapping register
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x80)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG register
* GPIO_INTERRUPT_SD mapping register
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
/** INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_SD_MAP_S 0
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_M (INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V << INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S)
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_GPIO_INTERRUPT_EXT_MAP_S 0
/** INTERRUPT_CORE0_PAU_INTR_MAP_REG register
* PAU_INTR mapping register
*/
#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
#define INTERRUPT_CORE0_PAU_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x84)
/** INTERRUPT_CORE0_PAU_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -434,7 +421,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG register
* HP_PERI_TIMEOUT_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
#define INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x88)
/** INTERRUPT_CORE0_HP_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -446,7 +433,7 @@ extern "C" {
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG register
* MODEM_PERI_TIMEOUT_INTR mapping register
*/
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
#define INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x8c)
/** INTERRUPT_CORE0_MODEM_PERI_TIMEOUT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -458,7 +445,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG register
* HP_APM_M0_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
#define INTERRUPT_CORE0_HP_APM_M0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x90)
/** INTERRUPT_CORE0_HP_APM_M0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -470,7 +457,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG register
* HP_APM_M1_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
#define INTERRUPT_CORE0_HP_APM_M1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x94)
/** INTERRUPT_CORE0_HP_APM_M1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -482,7 +469,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG register
* HP_APM_M2_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
#define INTERRUPT_CORE0_HP_APM_M2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x98)
/** INTERRUPT_CORE0_HP_APM_M2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -494,7 +481,7 @@ extern "C" {
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG register
* HP_APM_M3_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x9c)
/** INTERRUPT_CORE0_HP_APM_M3_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -503,6 +490,18 @@ extern "C" {
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M3_INTR_MAP_S 0
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG register
* HP_APM_M4_INTR mapping register
*/
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xa0)
/** INTERRUPT_CORE0_HP_APM_M4_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_M (INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V << INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S)
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_HP_APM_M4_INTR_MAP_S 0
/** INTERRUPT_CORE0_LP_APM0_INTR_MAP_REG register
* LP_APM0_INTR mapping register
*/
@ -527,17 +526,17 @@ extern "C" {
#define INTERRUPT_CORE0_MSPI_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_MSPI_INTR_MAP_S 0
/** INTERRUPT_CORE0_I2S1_INTR_MAP_REG register
* I2S1_INTR mapping register
/** INTERRUPT_CORE0_I2S_INTR_MAP_REG register
* I2S_INTR mapping register
*/
#define INTERRUPT_CORE0_I2S1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
/** INTERRUPT_CORE0_I2S1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_I2S_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xac)
/** INTERRUPT_CORE0_I2S_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_I2S1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_I2S1_INTR_MAP_M (INTERRUPT_CORE0_I2S1_INTR_MAP_V << INTERRUPT_CORE0_I2S1_INTR_MAP_S)
#define INTERRUPT_CORE0_I2S1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_I2S1_INTR_MAP_S 0
#define INTERRUPT_CORE0_I2S_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_I2S_INTR_MAP_M (INTERRUPT_CORE0_I2S_INTR_MAP_V << INTERRUPT_CORE0_I2S_INTR_MAP_S)
#define INTERRUPT_CORE0_I2S_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_I2S_INTR_MAP_S 0
/** INTERRUPT_CORE0_UHCI0_INTR_MAP_REG register
* UHCI0_INTR mapping register
@ -587,46 +586,70 @@ extern "C" {
#define INTERRUPT_CORE0_LEDC_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_LEDC_INTR_MAP_S 0
/** INTERRUPT_CORE0_CAN0_INTR_MAP_REG register
* CAN0_INTR mapping register
/** INTERRUPT_CORE0_TWAI0_INTR_MAP_REG register
* TWAI0_INTR mapping register
*/
#define INTERRUPT_CORE0_CAN0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
/** INTERRUPT_CORE0_CAN0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc0)
/** INTERRUPT_CORE0_TWAI0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_CAN0_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_CAN0_INTR_MAP_M (INTERRUPT_CORE0_CAN0_INTR_MAP_V << INTERRUPT_CORE0_CAN0_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_CAN0_INTR_MAP_S 0
#define INTERRUPT_CORE0_TWAI0_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_INTR_MAP_S 0
/** INTERRUPT_CORE0_CAN1_INTR_MAP_REG register
* CAN1_INTR mapping register
/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG register
* TWAI0_TIMER_INTR mapping register
*/
#define INTERRUPT_CORE0_CAN1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
/** INTERRUPT_CORE0_CAN1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc4)
/** INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_CAN1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_CAN1_INTR_MAP_M (INTERRUPT_CORE0_CAN1_INTR_MAP_V << INTERRUPT_CORE0_CAN1_INTR_MAP_S)
#define INTERRUPT_CORE0_CAN1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_CAN1_INTR_MAP_S 0
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI0_TIMER_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_INTR_MAP_REG register
* USB_INTR mapping register
/** INTERRUPT_CORE0_TWAI1_INTR_MAP_REG register
* TWAI1_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
/** INTERRUPT_CORE0_USB_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xc8)
/** INTERRUPT_CORE0_TWAI1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_INTR_MAP_M (INTERRUPT_CORE0_USB_INTR_MAP_V << INTERRUPT_CORE0_USB_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_INTR_MAP_S 0
#define INTERRUPT_CORE0_TWAI1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_INTR_MAP_S 0
/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG register
* TWAI1_TIMER_INTR mapping register
*/
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
/** INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_M (INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V << INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S)
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TWAI1_TIMER_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG register
* USB_SERIAL_JTAG_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
/** INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_M (INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V << INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_SERIAL_JTAG_INTR_MAP_S 0
/** INTERRUPT_CORE0_RMT_INTR_MAP_REG register
* RMT_INTR mapping register
*/
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xcc)
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
/** INTERRUPT_CORE0_RMT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -638,7 +661,7 @@ extern "C" {
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG register
* I2C_EXT0_INTR mapping register
*/
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd0)
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
/** INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -650,7 +673,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG register
* TG0_T0_INTR mapping register
*/
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd4)
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
/** INTERRUPT_CORE0_TG0_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -659,22 +682,10 @@ extern "C" {
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG0_T0_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG register
* TG0_T1_INTR mapping register
*/
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xd8)
/** INTERRUPT_CORE0_TG0_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_M (INTERRUPT_CORE0_TG0_T1_INTR_MAP_V << INTERRUPT_CORE0_TG0_T1_INTR_MAP_S)
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG0_T1_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG register
* TG0_WDT_INTR mapping register
*/
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xdc)
#define INTERRUPT_CORE0_TG0_WDT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
/** INTERRUPT_CORE0_TG0_WDT_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -686,7 +697,7 @@ extern "C" {
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG register
* TG1_T0_INTR mapping register
*/
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe0)
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
/** INTERRUPT_CORE0_TG1_T0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -695,18 +706,6 @@ extern "C" {
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG1_T0_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG register
* TG1_T1_INTR mapping register
*/
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0xe4)
/** INTERRUPT_CORE0_TG1_T1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_M (INTERRUPT_CORE0_TG1_T1_INTR_MAP_V << INTERRUPT_CORE0_TG1_T1_INTR_MAP_S)
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_TG1_T1_INTR_MAP_S 0
/** INTERRUPT_CORE0_TG1_WDT_INTR_MAP_REG register
* TG1_WDT_INTR mapping register
*/
@ -815,70 +814,10 @@ extern "C" {
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_PARL_IO_RX_INTR_MAP_S 0
/** INTERRUPT_CORE0_SLC0_INTR_MAP_REG register
* SLC0_INTR mapping register
*/
#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
/** INTERRUPT_CORE0_SLC0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_SLC0_INTR_MAP_M (INTERRUPT_CORE0_SLC0_INTR_MAP_V << INTERRUPT_CORE0_SLC0_INTR_MAP_S)
#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0
/** INTERRUPT_CORE0_SLC1_INTR_MAP_REG register
* SLC1_INTR mapping register
*/
#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/** INTERRUPT_CORE0_SLC1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_SLC1_INTR_MAP_M (INTERRUPT_CORE0_SLC1_INTR_MAP_V << INTERRUPT_CORE0_SLC1_INTR_MAP_S)
#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG register
* USB_OTG20_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/** INTERRUPT_CORE0_USB_OTG20_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG register
* USB_OTG20_MULTI_PROC_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/** INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MULTI_PROC_INTR_MAP_S 0
/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG register
* USB_OTG20_MISC_INTR mapping register
*/
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
/** INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_M (INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V << INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S)
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_USB_OTG20_MISC_INTR_MAP_S 0
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG register
* DMA_IN_CH0_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
#define INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10c)
/** INTERRUPT_CORE0_DMA_IN_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -890,7 +829,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG register
* DMA_IN_CH1_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
#define INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
/** INTERRUPT_CORE0_DMA_IN_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -902,7 +841,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG register
* DMA_IN_CH2_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
#define INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
/** INTERRUPT_CORE0_DMA_IN_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -914,7 +853,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG register
* DMA_OUT_CH0_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
#define INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
/** INTERRUPT_CORE0_DMA_OUT_CH0_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -926,7 +865,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG register
* DMA_OUT_CH1_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
#define INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11c)
/** INTERRUPT_CORE0_DMA_OUT_CH1_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -938,7 +877,7 @@ extern "C" {
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG register
* DMA_OUT_CH2_INTR mapping register
*/
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
#define INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
/** INTERRUPT_CORE0_DMA_OUT_CH2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -950,7 +889,7 @@ extern "C" {
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG register
* GPSPI2_INTR mapping register
*/
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
#define INTERRUPT_CORE0_GPSPI2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
/** INTERRUPT_CORE0_GPSPI2_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -962,7 +901,7 @@ extern "C" {
/** INTERRUPT_CORE0_AES_INTR_MAP_REG register
* AES_INTR mapping register
*/
#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
#define INTERRUPT_CORE0_AES_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
/** INTERRUPT_CORE0_AES_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -974,7 +913,7 @@ extern "C" {
/** INTERRUPT_CORE0_SHA_INTR_MAP_REG register
* SHA_INTR mapping register
*/
#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
#define INTERRUPT_CORE0_SHA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12c)
/** INTERRUPT_CORE0_SHA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -986,7 +925,7 @@ extern "C" {
/** INTERRUPT_CORE0_RSA_INTR_MAP_REG register
* RSA_INTR mapping register
*/
#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
#define INTERRUPT_CORE0_RSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
/** INTERRUPT_CORE0_RSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -998,7 +937,7 @@ extern "C" {
/** INTERRUPT_CORE0_ECC_INTR_MAP_REG register
* ECC_INTR mapping register
*/
#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
#define INTERRUPT_CORE0_ECC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
/** INTERRUPT_CORE0_ECC_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -1010,7 +949,7 @@ extern "C" {
/** INTERRUPT_CORE0_ECDSA_INTR_MAP_REG register
* ECDSA_INTR mapping register
*/
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
#define INTERRUPT_CORE0_ECDSA_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
/** INTERRUPT_CORE0_ECDSA_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -1022,7 +961,7 @@ extern "C" {
/** INTERRUPT_CORE0_KM_INTR_MAP_REG register
* KM_INTR mapping register
*/
#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
#define INTERRUPT_CORE0_KM_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13c)
/** INTERRUPT_CORE0_KM_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
@ -1031,10 +970,10 @@ extern "C" {
#define INTERRUPT_CORE0_KM_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_KM_INTR_MAP_S 0
/** INTERRUPT_CORE0_INT_STATUS_REG_0_REG register
/** INTERRUPT_CORE0_INT_STATUS_0_REG register
* Status register for interrupt sources 0 ~ 31
*/
#define INTERRUPT_CORE0_INT_STATUS_REG_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
#define INTERRUPT_CORE0_INT_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
/** INTERRUPT_CORE0_INT_STATUS_0 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources numbered from .Each bit corresponds
* to one interrupt source
@ -1046,10 +985,10 @@ extern "C" {
#define INTERRUPT_CORE0_INT_STATUS_0_V 0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_0_S 0
/** INTERRUPT_CORE0_INT_STATUS_REG_1_REG register
/** INTERRUPT_CORE0_INT_STATUS_1_REG register
* Status register for interrupt sources 32 ~ 63
*/
#define INTERRUPT_CORE0_INT_STATUS_REG_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
#define INTERRUPT_CORE0_INT_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
/** INTERRUPT_CORE0_INT_STATUS_1 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources numbered from .Each bit corresponds
* to one interrupt source
@ -1061,10 +1000,10 @@ extern "C" {
#define INTERRUPT_CORE0_INT_STATUS_1_V 0xFFFFFFFFU
#define INTERRUPT_CORE0_INT_STATUS_1_S 0
/** INTERRUPT_CORE0_INT_STATUS_REG_2_REG register
/** INTERRUPT_CORE0_INT_STATUS_2_REG register
* Status register for interrupt sources 64 ~ 95
*/
#define INTERRUPT_CORE0_INT_STATUS_REG_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15c)
#define INTERRUPT_CORE0_INT_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
/** INTERRUPT_CORE0_INT_STATUS_2 : RO; bitpos: [31:0]; default: 0;
* Represents the status of the interrupt sources numbered from .Each bit corresponds
* to one interrupt source
@ -1079,7 +1018,7 @@ extern "C" {
/** INTERRUPT_CORE0_CLOCK_GATE_REG register
* Interrupt clock gating configure register
*/
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14c)
/** INTERRUPT_CORE0_REG_CLK_EN : R/W; bitpos: [0]; default: 0;
* Interrupt clock gating configure register
*/
@ -1092,7 +1031,7 @@ extern "C" {
* Version control register
*/
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7fc)
/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36717104;
/** INTERRUPT_CORE0_INTERRUPT_DATE : R/W; bitpos: [27:0]; default: 36773985;
* Version control register
*/
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFFU

2
components/soc/esp32c5/beta3/include/soc/interrupt_reg.h
View File

@ -16,8 +16,8 @@ extern "C" {
* ESP32C5 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
*/
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
/* We only have a single core on the C5, CORE0 */
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG
#ifdef __cplusplus

106
components/soc/esp32c5/beta3/include/soc/interrupts.h
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -12,25 +12,24 @@ extern "C"
{
#endif
// TODO: [ESP32C5] IDF-8654 need update for MP version
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_WIFI_MAC_INTR_SOURCE,
ETS_WIFI_MAC_NMI_SOURCE,
ETS_WIFI_PWR_INTR_SOURCE,
ETS_WIFI_BB_INTR_SOURCE,
ETS_BT_MAC_INTR_SOURCE,
ETS_BT_BB_INTR_SOURCE,
ETS_BT_BB_NMI_SOURCE,
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibration*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
ETS_LP_TIMER_INTR_SOURCE,
ETS_COEX_INTR_SOURCE,
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MST_INTR_SOURCE,
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_ZB_MAC_INTR_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_TIMER_INTR_SOURCE,
ETS_LP_UART_INTR_SOURCE,
ETS_LP_I2C_INTR_SOURCE,
@ -39,17 +38,16 @@ typedef enum {
ETS_LP_APM_M0_INTR_SOURCE,
ETS_LP_APM_M1_INTR_SOURCE,
ETS_HUK_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE,
ETS_FROM_CPU_INTR1_SOURCE,
ETS_FROM_CPU_INTR2_SOURCE,
ETS_FROM_CPU_INTR3_SOURCE,
ETS_ASSIST_DEBUG_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
ETS_TRACE_INTR_SOURCE,
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE,
ETS_GPIO_NMI_SOURCE,
ETS_GPIO_PAD_COMP_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
@ -57,52 +55,48 @@ typedef enum {
ETS_HP_APM_M1_INTR_SOURCE,
ETS_HP_APM_M2_INTR_SOURCE,
ETS_HP_APM_M3_INTR_SOURCE,
ETS_HP_APM_M4_INTR_SOURCE,
ETS_LP_APM0_INTR_SOURCE,
ETS_MSPI_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE,
ETS_UHCI0_INTR_SOURCE,
ETS_UART0_INTR_SOURCE,
ETS_UART1_INTR_SOURCE,
ETS_LEDC_INTR_SOURCE,
ETS_TWAI0_INTR_SOURCE,
ETS_TWAI1_INTR_SOURCE,
ETS_USB_INTR_SOURCE,
ETS_RMT_INTR_SOURCE,
ETS_I2C_EXT0_INTR_SOURCE,
ETS_TG0_T0_LEVEL_INTR_SOURCE,
ETS_TG0_T1_LEVEL_INTR_SOURCE,
ETS_TG0_WDT_LEVEL_INTR_SOURCE,
ETS_TG1_T0_LEVEL_INTR_SOURCE,
ETS_TG1_T1_LEVEL_INTR_SOURCE,
ETS_TG1_WDT_LEVEL_INTR_SOURCE,
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
ETS_APB_ADC_INTR_SOURCE,
ETS_PWM_INTR_SOURCE,
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
ETS_TWAI0_INTR_SOURCE, /**< interrupt of can0, level*/
ETS_TWAI0_TIMER_INTR_SOURCE, /**< interrupt of can0 timer, level*/
ETS_TWAI1_INTR_SOURCE, /**< interrupt of can1, level*/
ETS_TWAI1_TIMER_INTR_SOURCE, /**< interrupt of can0 timer, level*/
ETS_USB_SERIAL_JTAG_INTR_SOURCE, /**< interrupt of USB, level*/
ETS_RMT_INTR_SOURCE, /**< interrupt of remote controller, level*/
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
ETS_TG0_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, level*/
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, level*/
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level*/
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
ETS_PARL_IO_RX_INTR_SOURCE,
ETS_SLC0_INTR_SOURCE,
ETS_SLC1_INTR_SOURCE,
ETS_USB_OTG20_INTR_SOURCE,
ETS_USB_OTG20_MULTI_PROC_INTR_SOURCE,
ETS_USB_OTG20_MISC_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE,
ETS_DMA_IN_CH1_INTR_SOURCE,
ETS_DMA_IN_CH2_INTR_SOURCE,
ETS_DMA_OUT_CH0_INTR_SOURCE,
ETS_DMA_OUT_CH1_INTR_SOURCE,
ETS_DMA_OUT_CH2_INTR_SOURCE,
ETS_DMA_IN_CH0_INTR_SOURCE, /**< interrupt of general DMA IN channel 0, LEVEL*/
ETS_DMA_IN_CH1_INTR_SOURCE, /**< interrupt of general DMA IN channel 1, LEVEL*/
ETS_DMA_IN_CH2_INTR_SOURCE, /**< interrupt of general DMA IN channel 2, LEVEL*/
ETS_DMA_OUT_CH0_INTR_SOURCE, /**< interrupt of general DMA OUT channel 0, LEVEL*/
ETS_DMA_OUT_CH1_INTR_SOURCE, /**< interrupt of general DMA OUT channel 1, LEVEL*/
ETS_DMA_OUT_CH2_INTR_SOURCE, /**< interrupt of general DMA OUT channel 2, LEVEL*/
ETS_GPSPI2_INTR_SOURCE,
ETS_AES_INTR_SOURCE,
ETS_SHA_INTR_SOURCE,
ETS_RSA_INTR_SOURCE,
ETS_ECC_INTR_SOURCE,
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
ETS_ECC_INTR_SOURCE, /**< interrupt of ECC accelerator, level*/
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
} periph_interrupt_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];

169
components/soc/esp32c5/beta3/interrupts.c
View File

@ -1,97 +1,90 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
// TODO: [ESP32C5] IDF-8654 need update for MP version
const char *const esp_isr_names[] = {
[0] = "WIFI_MAC",
[1] = "WIFI_MAC_NMI",
[2] = "WIFI_PWR",
[3] = "WIFI_BB",
[4] = "BT_MAC",
[5] = "BT_BB",
[6] = "BT_BB_NMI",
[7] = "LP_TIMER",
[8] = "COEX",
[9] = "BLE_TIMER",
[10] = "BLE_SEC",
[11] = "I2C_MASTER",
[12] = "ZB_MAC",
[13] = "PMU",
[14] = "EFUSE",
[15] = "LP_RTC_TIMER",
[16] = "LP_UART",
[17] = "LP_I2C",
[18] = "LP_WDT",
[19] = "LP_PERI_TIMEOUT",
[20] = "LP_APM_M0",
[21] = "LP_APM_M1",
[22] = "HUK",
[23] = "CPU_FROM_CPU_0",
[24] = "CPU_FROM_CPU_1",
[25] = "CPU_FROM_CPU_2",
[26] = "CPU_FROM_CPU_3",
[27] = "ASSIST_DEBUG",
[28] = "TRACE",
[29] = "CACHE",
[30] = "CPU_PERI_TIMEOUT",
[31] = "GPIO_INTERRUPT_PRO",
[32] = "GPIO_INTERRUPT_PRO_NMI",
[33] = "GPIO_INTERRUPT_SD",
[34] = "PAU",
[35] = "HP_PERI_TIMEOUT",
[36] = "MODEM_PERI_TIMEOUT",
[37] = "HP_APM_M0",
[38] = "HP_APM_M1",
[39] = "HP_APM_M2",
[40] = "HP_APM_M3",
[41] = "LP_APM0",
[42] = "MSPI",
[43] = "I2S1",
[44] = "UHCI0",
[45] = "UART0",
[46] = "UART1",
[47] = "LEDC",
[48] = "TWAI0",
[49] = "TWAI1",
[50] = "USB",
[51] = "RMT",
[52] = "I2C_EXT0",
[53] = "TG0_T0",
[54] = "TG0_T1",
[55] = "TG0_WDT",
[56] = "TG1_T0",
[57] = "TG1_T1",
[58] = "TG1_WDT",
[59] = "SYSTIMER_TARGET0",
[60] = "SYSTIMER_TARGET1",
[61] = "SYSTIMER_TARGET2",
[62] = "APB_ADC",
[63] = "PWM",
[64] = "PCNT",
[65] = "PARL_IO_TX",
[66] = "PARL_IO_RX",
[67] = "SLC0",
[68] = "SLC1",
[69] = "USB_OTG20",
[70] = "USB_OTG20_MULTI_PROC",
[71] = "USB_OTG20_MISC",
[72] = "DMA_IN_CH0",
[73] = "DMA_IN_CH1",
[74] = "DMA_IN_CH2",
[75] = "DMA_OUT_CH0",
[76] = "DMA_OUT_CH1",
[77] = "DMA_OUT_CH2",
[78] = "GPSPI2",
[79] = "AES",
[80] = "SHA",
[81] = "RSA",
[82] = "ECC",
[83] = "ECDSA",
[84] = "KM",
[ETS_WIFI_MAC_INTR_SOURCE] = "WIFI_MAC",
[ETS_WIFI_MAC_NMI_SOURCE] = "WIFI_MAC_NMI",
[ETS_WIFI_PWR_INTR_SOURCE] = "WIFI_PWR",
[ETS_WIFI_BB_INTR_SOURCE] = "WIFI_BB",
[ETS_BT_MAC_INTR_SOURCE] = "BT_MAC",
[ETS_BT_BB_INTR_SOURCE] = "BT_BB",
[ETS_BT_BB_NMI_SOURCE] = "BT_BB_NMI",
[ETS_LP_TIMER_INTR_SOURCE] = "LP_TIMER",
[ETS_COEX_INTR_SOURCE] = "COEX",
[ETS_BLE_TIMER_INTR_SOURCE] = "BLE_TIMER",
[ETS_BLE_SEC_INTR_SOURCE] = "BLE_SEC",
[ETS_I2C_MASTER_SOURCE] = "I2C_MASTER",
[ETS_ZB_MAC_INTR_SOURCE] = "ZB_MAC",
[ETS_PMU_INTR_SOURCE] = "PMU",
[ETS_EFUSE_INTR_SOURCE] = "EFUSE",
[ETS_LP_RTC_TIMER_INTR_SOURCE] = "LP_RTC_TIMER",
[ETS_LP_UART_INTR_SOURCE] = "LP_UART",
[ETS_LP_I2C_INTR_SOURCE] = "LP_I2C",
[ETS_LP_WDT_INTR_SOURCE] = "LP_WDT",
[ETS_LP_PERI_TIMEOUT_INTR_SOURCE] = "LP_PERI_TIMEOUT",
[ETS_LP_APM_M0_INTR_SOURCE] = "LP_APM_M0",
[ETS_LP_APM_M1_INTR_SOURCE] = "LP_APM_M1",
[ETS_HUK_INTR_SOURCE] = "HUK",
[ETS_FROM_CPU_INTR0_SOURCE] = "FROM_CPU_INTR0",
[ETS_FROM_CPU_INTR1_SOURCE] = "FROM_CPU_INTR1",
[ETS_FROM_CPU_INTR2_SOURCE] = "FROM_CPU_INTR2",
[ETS_FROM_CPU_INTR3_SOURCE] = "FROM_CPU_INTR3",
[ETS_ASSIST_DEBUG_INTR_SOURCE] = "ASSIST_DEBUG",
[ETS_TRACE_INTR_SOURCE] = "TRACE",
[ETS_CACHE_INTR_SOURCE] = "CACHE",
[ETS_CPU_PERI_TIMEOUT_INTR_SOURCE] = "CPU_PERI_TIMEOUT",
[ETS_GPIO_INTR_SOURCE] = "GPIO_INTR",
[ETS_GPIO_NMI_SOURCE] = "GPIO_NMI",
[ETS_PAU_INTR_SOURCE] = "PAU",
[ETS_HP_PERI_TIMEOUT_INTR_SOURCE] = "HP_PERI_TIMEOUT",
[ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE] = "MODEM_PERI_TIMEOUT",
[ETS_HP_APM_M0_INTR_SOURCE] = "HP_APM_M0",
[ETS_HP_APM_M1_INTR_SOURCE] = "HP_APM_M1",
[ETS_HP_APM_M2_INTR_SOURCE] = "HP_APM_M2",
[ETS_HP_APM_M3_INTR_SOURCE] = "HP_APM_M3",
[ETS_HP_APM_M4_INTR_SOURCE] = "HP_APM_M4",
[ETS_LP_APM0_INTR_SOURCE] = "LP_APM0",
[ETS_MSPI_INTR_SOURCE] = "MSPI",
[ETS_I2S1_INTR_SOURCE] = "I2S1",
[ETS_UHCI0_INTR_SOURCE] = "UHCI0",
[ETS_UART0_INTR_SOURCE] = "UART0",
[ETS_UART1_INTR_SOURCE] = "UART1",
[ETS_LEDC_INTR_SOURCE] = "LEDC",
[ETS_TWAI0_INTR_SOURCE] = "TWAI0",
[ETS_TWAI0_TIMER_INTR_SOURCE] = "TWAI0_TIMER",
[ETS_TWAI1_INTR_SOURCE] = "TWAI1",
[ETS_TWAI1_TIMER_INTR_SOURCE] = "TWAI1_TIMER",
[ETS_USB_SERIAL_JTAG_INTR_SOURCE] = "USB_SERIAL_JTAG",
[ETS_RMT_INTR_SOURCE] = "RMT",
[ETS_I2C_EXT0_INTR_SOURCE] = "I2C_EXT0",
[ETS_TG0_T0_LEVEL_INTR_SOURCE] = "TG0_T0_LEVEL",
[ETS_TG0_WDT_LEVEL_INTR_SOURCE] = "TG0_WDT_LEVEL",
[ETS_TG1_T0_LEVEL_INTR_SOURCE] = "TG1_T0_LEVEL",
[ETS_TG1_WDT_LEVEL_INTR_SOURCE] = "TG1_WDT_LEVEL",
[ETS_SYSTIMER_TARGET0_INTR_SOURCE] = "SYSTIMER_TARGET0",
[ETS_SYSTIMER_TARGET1_INTR_SOURCE] = "SYSTIMER_TARGET1",
[ETS_SYSTIMER_TARGET2_INTR_SOURCE] = "SYSTIMER_TARGET2",
[ETS_APB_ADC_INTR_SOURCE] = "APB_ADC",
[ETS_MCPWM0_INTR_SOURCE] = "MCPWM0",
[ETS_PCNT_INTR_SOURCE] = "PCNT",
[ETS_PARL_IO_TX_INTR_SOURCE] = "PARL_IO_TX",
[ETS_PARL_IO_RX_INTR_SOURCE] = "PARL_IO_RX",
[ETS_DMA_IN_CH0_INTR_SOURCE] = "DMA_IN_CH0",
[ETS_DMA_IN_CH1_INTR_SOURCE] = "DMA_IN_CH1",
[ETS_DMA_IN_CH2_INTR_SOURCE] = "DMA_IN_CH2",
[ETS_DMA_OUT_CH0_INTR_SOURCE] = "DMA_OUT_CH0",
[ETS_DMA_OUT_CH1_INTR_SOURCE] = "DMA_OUT_CH1",
[ETS_DMA_OUT_CH2_INTR_SOURCE] = "DMA_OUT_CH2",
[ETS_GPSPI2_INTR_SOURCE] = "GPSPI2",
[ETS_AES_INTR_SOURCE] = "AES",
[ETS_SHA_INTR_SOURCE] = "SHA",
[ETS_RSA_INTR_SOURCE] = "RSA",
[ETS_ECC_INTR_SOURCE] = "ECC",
[ETS_ECDSA_INTR_SOURCE] = "ECDSA",
[ETS_KM_INTR_SOURCE] = "KM"
};

16
components/soc/esp32c5/mp/include/soc/interrupt_matrix_reg.h
View File

@ -335,17 +335,17 @@ extern "C" {
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG register
* BUS_MONITOR_INTR mapping register
/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG register
* ASSIST_DEBUG_INTR mapping register
*/
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
/** INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x6c)
/** INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W; bitpos: [5:0]; default: 0;
* Configures the interrupt source into one CPU interrupt.
*/
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_M (INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V << INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S)
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_BUS_MONITOR_INTR_MAP_S 0
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000003FU
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V << INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x0000003FU
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
/** INTERRUPT_CORE0_TRACE_INTR_MAP_REG register
* TRACE_INTR mapping register

18
components/soc/esp32c5/mp/include/soc/interrupt_reg.h
View File

@ -1,11 +1,25 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* ESP32C5 uses the CLIC controller as the interrupt controller (SOC_INT_CLIC_SUPPORTED = y)
*/
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
/* We only have a single core on the C5, CORE0 */
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG INTERRUPT_CURRENT_CORE_INT_THRESH_REG
#ifdef __cplusplus
}
#endif

20
components/soc/esp32c5/mp/include/soc/interrupts.h
View File

@ -1,11 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
@ -19,7 +18,7 @@ typedef enum {
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
ETS_WIFI_PWR_INTR_SOURCE, /**< */
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibration*/
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
@ -28,7 +27,7 @@ typedef enum {
ETS_BLE_TIMER_INTR_SOURCE,
ETS_BLE_SEC_INTR_SOURCE,
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
ETS_ZB_MAC_SOURCE,
ETS_ZB_MAC_INTR_SOURCE,
ETS_PMU_INTR_SOURCE,
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
ETS_LP_RTC_TIMER_INTR_SOURCE,
@ -39,8 +38,8 @@ typedef enum {
ETS_LP_APM_M0_INTR_SOURCE,
ETS_LP_APM_M1_INTR_SOURCE,
ETS_HUK_INTR_SOURCE,
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
ETS_FROM_CPU_INTR0_SOURCE, /**< interrupt0 generated from a CPU, level*/
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
@ -48,7 +47,7 @@ typedef enum {
ETS_CACHE_INTR_SOURCE,
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
ETS_GPIO_INTR_EXT_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
ETS_PAU_INTR_SOURCE,
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE,
@ -78,10 +77,7 @@ typedef enum {
ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< interrupt of system timer 0 */
ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< interrupt of system timer 1 */
ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< interrupt of system timer 2 */
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET0_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET0_INTR_SOURCE */
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET1_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET1_INTR_SOURCE */
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE = ETS_SYSTIMER_TARGET2_INTR_SOURCE, /**< use ETS_SYSTIMER_TARGET2_INTR_SOURCE */
ETS_APB_ADC_INTR_SOURCE = 62, /**< interrupt of APB ADC, LEVEL*/
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
ETS_MCPWM0_INTR_SOURCE, /**< interrupt of MCPWM0, LEVEL*/
ETS_PCNT_INTR_SOURCE,
ETS_PARL_IO_TX_INTR_SOURCE,
@ -100,7 +96,7 @@ typedef enum {
ETS_ECDSA_INTR_SOURCE,
ETS_KM_INTR_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrput_t;
} periph_interrupt_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];

162
components/soc/esp32c5/mp/interrupts.c
View File

@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@ -7,84 +7,84 @@
#include "soc/interrupts.h"
const char *const esp_isr_names[] = {
[0] = "WIFI_MAC",
[1] = "WIFI_MAC_NMI",
[2] = "WIFI_PWR",
[3] = "WIFI_BB",
[4] = "BT_MAC",
[5] = "BT_BB",
[6] = "BT_BB_NMI",
[7] = "LP_TIMER",
[8] = "COEX",
[9] = "BLE_TIMER",
[10] = "BLE_SEC",
[11] = "I2C_MASTER",
[12] = "ZB_MAC",
[13] = "PMU",
[14] = "EFUSE",
[15] = "LP_RTC_TIMER",
[16] = "LP_UART",
[17] = "LP_I2C",
[18] = "LP_WDT",
[19] = "LP_PERI_TIMEOUT",
[20] = "LP_APM_M0",
[21] = "LP_APM_M1",
[22] = "HUK",
[23] = "CPU_FROM_CPU_0",
[24] = "CPU_FROM_CPU_1",
[25] = "CPU_FROM_CPU_2",
[26] = "CPU_FROM_CPU_3",
[27] = "ASSIST_DEBUG",
[28] = "TRACE",
[29] = "CACHE",
[30] = "CPU_PERI_TIMEOUT",
[31] = "GPIO_INTERRUPT_PRO",
[32] = "GPIO_INTERRUPT_EXT",
[33] = "PAU",
[34] = "HP_PERI_TIMEOUT",
[35] = "MODEM_PERI_TIMEOUT",
[36] = "HP_APM_M0",
[37] = "HP_APM_M1",
[38] = "HP_APM_M2",
[39] = "HP_APM_M3",
[40] = "HP_APM_M4",
[41] = "LP_APM0",
[42] = "MSPI",
[43] = "I2S",
[44] = "UHCI0",
[45] = "UART0",
[46] = "UART1",
[47] = "LEDC",
[48] = "TWAI0",
[49] = "TWAI0_TIMER",
[50] = "TWAI1",
[51] = "TWAI1_TIMER",
[52] = "USB_SERIAL_JTAG",
[53] = "RMT",
[54] = "I2C_EXT0",
[55] = "TG0_T0",
[56] = "TG0_WDT",
[57] = "TG1_T0",
[58] = "TG1_WDT",
[59] = "SYSTIMER_TARGET0",
[60] = "SYSTIMER_TARGET1",
[61] = "SYSTIMER_TARGET2",
[62] = "APB_ADC",
[63] = "PWM",
[64] = "PCNT",
[65] = "PARL_IO_TX",
[66] = "PARL_IO_RX",
[67] = "DMA_IN_CH0",
[68] = "DMA_IN_CH1",
[69] = "DMA_IN_CH2",
[70] = "DMA_OUT_CH0",
[71] = "DMA_OUT_CH1",
[72] = "DMA_OUT_CH2",
[73] = "GPSPI2",
[74] = "AES",
[75] = "SHA",
[76] = "RSA",
[77] = "ECC",
[78] = "ECDSA",
[79] = "KM",
[ETS_WIFI_MAC_INTR_SOURCE] = "WIFI_MAC",
[ETS_WIFI_MAC_NMI_SOURCE] = "WIFI_MAC_NMI",
[ETS_WIFI_PWR_INTR_SOURCE] = "WIFI_PWR",
[ETS_WIFI_BB_INTR_SOURCE] = "WIFI_BB",
[ETS_BT_MAC_INTR_SOURCE] = "BT_MAC",
[ETS_BT_BB_INTR_SOURCE] = "BT_BB",
[ETS_BT_BB_NMI_SOURCE] = "BT_BB_NMI",
[ETS_LP_TIMER_INTR_SOURCE] = "LP_TIMER",
[ETS_COEX_INTR_SOURCE] = "COEX",
[ETS_BLE_TIMER_INTR_SOURCE] = "BLE_TIMER",
[ETS_BLE_SEC_INTR_SOURCE] = "BLE_SEC",
[ETS_I2C_MASTER_SOURCE] = "I2C_MASTER",
[ETS_ZB_MAC_INTR_SOURCE] = "ZB_MAC",
[ETS_PMU_INTR_SOURCE] = "PMU",
[ETS_EFUSE_INTR_SOURCE] = "EFUSE",
[ETS_LP_RTC_TIMER_INTR_SOURCE] = "LP_RTC_TIMER",
[ETS_LP_UART_INTR_SOURCE] = "LP_UART",
[ETS_LP_I2C_INTR_SOURCE] = "LP_I2C",
[ETS_LP_WDT_INTR_SOURCE] = "LP_WDT",
[ETS_LP_PERI_TIMEOUT_INTR_SOURCE] = "LP_PERI_TIMEOUT",
[ETS_LP_APM_M0_INTR_SOURCE] = "LP_APM_M0",
[ETS_LP_APM_M1_INTR_SOURCE] = "LP_APM_M1",
[ETS_HUK_INTR_SOURCE] = "HUK",
[ETS_FROM_CPU_INTR0_SOURCE] = "FROM_CPU_INTR0",
[ETS_FROM_CPU_INTR1_SOURCE] = "FROM_CPU_INTR1",
[ETS_FROM_CPU_INTR2_SOURCE] = "FROM_CPU_INTR2",
[ETS_FROM_CPU_INTR3_SOURCE] = "FROM_CPU_INTR3",
[ETS_ASSIST_DEBUG_INTR_SOURCE] = "ASSIST_DEBUG",
[ETS_TRACE_INTR_SOURCE] = "TRACE",
[ETS_CACHE_INTR_SOURCE] = "CACHE",
[ETS_CPU_PERI_TIMEOUT_INTR_SOURCE] = "CPU_PERI_TIMEOUT",
[ETS_GPIO_INTR_SOURCE] = "GPIO_INTR",
[ETS_GPIO_NMI_SOURCE] = "GPIO_NMI",
[ETS_PAU_INTR_SOURCE] = "PAU",
[ETS_HP_PERI_TIMEOUT_INTR_SOURCE] = "HP_PERI_TIMEOUT",
[ETS_MODEM_PERI_TIMEOUT_INTR_SOURCE] = "MODEM_PERI_TIMEOUT",
[ETS_HP_APM_M0_INTR_SOURCE] = "HP_APM_M0",
[ETS_HP_APM_M1_INTR_SOURCE] = "HP_APM_M1",
[ETS_HP_APM_M2_INTR_SOURCE] = "HP_APM_M2",
[ETS_HP_APM_M3_INTR_SOURCE] = "HP_APM_M3",
[ETS_HP_APM_M4_INTR_SOURCE] = "HP_APM_M4",
[ETS_LP_APM0_INTR_SOURCE] = "LP_APM0",
[ETS_MSPI_INTR_SOURCE] = "MSPI",
[ETS_I2S1_INTR_SOURCE] = "I2S1",
[ETS_UHCI0_INTR_SOURCE] = "UHCI0",
[ETS_UART0_INTR_SOURCE] = "UART0",
[ETS_UART1_INTR_SOURCE] = "UART1",
[ETS_LEDC_INTR_SOURCE] = "LEDC",
[ETS_TWAI0_INTR_SOURCE] = "TWAI0",
[ETS_TWAI0_TIMER_INTR_SOURCE] = "TWAI0_TIMER",
[ETS_TWAI1_INTR_SOURCE] = "TWAI1",
[ETS_TWAI1_TIMER_INTR_SOURCE] = "TWAI1_TIMER",
[ETS_USB_SERIAL_JTAG_INTR_SOURCE] = "USB_SERIAL_JTAG",
[ETS_RMT_INTR_SOURCE] = "RMT",
[ETS_I2C_EXT0_INTR_SOURCE] = "I2C_EXT0",
[ETS_TG0_T0_LEVEL_INTR_SOURCE] = "TG0_T0_LEVEL",
[ETS_TG0_WDT_LEVEL_INTR_SOURCE] = "TG0_WDT_LEVEL",
[ETS_TG1_T0_LEVEL_INTR_SOURCE] = "TG1_T0_LEVEL",
[ETS_TG1_WDT_LEVEL_INTR_SOURCE] = "TG1_WDT_LEVEL",
[ETS_SYSTIMER_TARGET0_INTR_SOURCE] = "SYSTIMER_TARGET0",
[ETS_SYSTIMER_TARGET1_INTR_SOURCE] = "SYSTIMER_TARGET1",
[ETS_SYSTIMER_TARGET2_INTR_SOURCE] = "SYSTIMER_TARGET2",
[ETS_APB_ADC_INTR_SOURCE] = "APB_ADC",
[ETS_MCPWM0_INTR_SOURCE] = "MCPWM0",
[ETS_PCNT_INTR_SOURCE] = "PCNT",
[ETS_PARL_IO_TX_INTR_SOURCE] = "PARL_IO_TX",
[ETS_PARL_IO_RX_INTR_SOURCE] = "PARL_IO_RX",
[ETS_DMA_IN_CH0_INTR_SOURCE] = "DMA_IN_CH0",
[ETS_DMA_IN_CH1_INTR_SOURCE] = "DMA_IN_CH1",
[ETS_DMA_IN_CH2_INTR_SOURCE] = "DMA_IN_CH2",
[ETS_DMA_OUT_CH0_INTR_SOURCE] = "DMA_OUT_CH0",
[ETS_DMA_OUT_CH1_INTR_SOURCE] = "DMA_OUT_CH1",
[ETS_DMA_OUT_CH2_INTR_SOURCE] = "DMA_OUT_CH2",
[ETS_GPSPI2_INTR_SOURCE] = "GPSPI2",
[ETS_AES_INTR_SOURCE] = "AES",
[ETS_SHA_INTR_SOURCE] = "SHA",
[ETS_RSA_INTR_SOURCE] = "RSA",
[ETS_ECC_INTR_SOURCE] = "ECC",
[ETS_ECDSA_INTR_SOURCE] = "ECDSA",
[ETS_KM_INTR_SOURCE] = "KM"
};