diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index 8ed1726e67..c049ecbe04 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -198,18 +198,12 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Flush(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED uint32_t autoload = Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache uint32_t autoload = Cache_Suspend_DCache(); Cache_Invalidate_DCache_All(); -#elif CONFIG_IDF_TARGET_ESP32C3 - uint32_t autoload = Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); -#elif CONFIG_IDF_TARGET_ESP32H2 - uint32_t autoload = Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); #endif ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x", src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned ); @@ -217,34 +211,26 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count); #elif CONFIG_IDF_TARGET_ESP32S2 int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0); -#else // S3, C3, H2 +#else int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0); #endif if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e); #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache Cache_Resume_DCache(autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 - Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32H2 - Cache_Resume_ICache(autoload); #endif return NULL; } #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache Cache_Resume_DCache(autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 - Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32H2 - Cache_Resume_ICache(autoload); #endif mapped = true; @@ -260,24 +246,15 @@ void bootloader_munmap(const void *mapping) Cache_Read_Disable(0); Cache_Flush(0); mmu_init(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED //TODO, save the autoload value. Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); Cache_MMU_Init(); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache Cache_Suspend_DCache(); Cache_Invalidate_DCache_All(); Cache_MMU_Init(); -#elif CONFIG_IDF_TARGET_ESP32C3 - //TODO, save the autoload value. - Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); - Cache_MMU_Init(); -#elif CONFIG_IDF_TARGET_ESP32H2 - Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); - Cache_MMU_Init(); #endif mapped = false; current_read_mapping = UINT32_MAX; @@ -303,26 +280,18 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Flush(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED uint32_t autoload = Cache_Suspend_ICache(); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache uint32_t autoload = Cache_Suspend_DCache(); -#elif CONFIG_IDF_TARGET_ESP32C3 - uint32_t autoload = Cache_Suspend_ICache(); -#elif CONFIG_IDF_TARGET_ESP32H2 - uint32_t autoload = Cache_Suspend_ICache(); #endif esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size); #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache Cache_Resume_DCache(autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 - Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32H2 - Cache_Resume_ICache(autoload); #endif return spi_to_esp_err(r); @@ -341,57 +310,39 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Flush(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED uint32_t autoload = Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache uint32_t autoload = Cache_Suspend_DCache(); Cache_Invalidate_DCache_All(); -#elif CONFIG_IDF_TARGET_ESP32C3 - uint32_t autoload = Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); -#elif CONFIG_IDF_TARGET_ESP32H2 - uint32_t autoload = Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); #endif ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping); #if CONFIG_IDF_TARGET_ESP32 int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1); #elif CONFIG_IDF_TARGET_ESP32S2 int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0); -#elif CONFIG_IDF_TARGET_ESP32S3 - int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0); -#elif CONFIG_IDF_TARGET_ESP32C3 - int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0); -#elif CONFIG_IDF_TARGET_ESP32H2 +#else // map rodata with DBus int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0); #endif if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e); #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache Cache_Resume_DCache(autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 - Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32H2 - Cache_Resume_ICache(autoload); #endif return ESP_FAIL; } current_read_mapping = map_at; #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache Cache_Resume_DCache(autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 - Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32H2 - Cache_Resume_ICache(autoload); #endif } map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at)); diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 8533f2b3ce..a4df6d9e1a 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -705,18 +705,12 @@ static void set_cache_and_start_app( #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Disable(0); Cache_Flush(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED uint32_t autoload = Cache_Suspend_ICache(); Cache_Invalidate_ICache_All(); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache uint32_t autoload = Cache_Suspend_DCache(); Cache_Invalidate_DCache_All(); -#elif CONFIG_IDF_TARGET_ESP32C3 - uint32_t autoload = Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); -#elif CONFIG_IDF_TARGET_ESP32H2 - uint32_t autoload = Cache_Suspend_ICache(); - Cache_Invalidate_ICache_All(); #endif /* Clear the MMU entries that are already set up, @@ -739,11 +733,7 @@ static void set_cache_and_start_app( rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count); #elif CONFIG_IDF_TARGET_ESP32S2 rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0); -#elif CONFIG_IDF_TARGET_ESP32S3 - rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0); -#elif CONFIG_IDF_TARGET_ESP32C3 - rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0); -#elif CONFIG_IDF_TARGET_ESP32H2 +#else // map rodata with DBUS rc = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count, 0); #endif ESP_LOGV(TAG, "rc=%d", rc); @@ -757,7 +747,8 @@ static void set_cache_and_start_app( irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count); #if CONFIG_IDF_TARGET_ESP32 rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count); -#elif CONFIG_IDF_TARGET_ESP32S2 +#else // access text with IBUS +#if CONFIG_IDF_TARGET_ESP32S2 uint32_t iram1_used = 0; if (irom_load_addr + irom_size > IRAM1_ADDRESS_LOW) { iram1_used = 1; @@ -767,12 +758,7 @@ static void set_cache_and_start_app( rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1); REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1); } - rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); -#elif CONFIG_IDF_TARGET_ESP32S3 - rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); -#elif CONFIG_IDF_TARGET_ESP32C3 - rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); -#elif CONFIG_IDF_TARGET_ESP32H2 +#endif rc = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count, 0); #endif ESP_LOGV(TAG, "rc=%d", rc); @@ -794,23 +780,16 @@ static void set_cache_and_start_app( #if !CONFIG_FREERTOS_UNICORE REG_CLR_BIT(EXTMEM_DCACHE_CTRL1_REG, EXTMEM_DCACHE_SHUT_CORE1_BUS); #endif -#elif CONFIG_IDF_TARGET_ESP32C3 - REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); - REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); -#elif CONFIG_IDF_TARGET_ESP32H2 +#else // ESP32C3, ESP32H2 REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS); REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS); #endif #if CONFIG_IDF_TARGET_ESP32 Cache_Read_Enable(0); -#elif CONFIG_IDF_TARGET_ESP32S2 +#elif SOC_ICACHE_ACCESS_RODATA_SUPPORTED Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32S3 +#else // access rodata with DCache Cache_Resume_DCache(autoload); -#elif CONFIG_IDF_TARGET_ESP32C3 - Cache_Resume_ICache(autoload); -#elif CONFIG_IDF_TARGET_ESP32H2 - Cache_Resume_ICache(autoload); #endif // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index 0406c5665a..ef4f2eb9b5 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -5,6 +5,7 @@ #pragma once +/*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_CPU_CORES_NUM 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 @@ -17,13 +18,10 @@ #define SOC_TEMP_SENSOR_SUPPORTED 1 #define SOC_FLASH_ENCRYPTION_XTS_AES 1 #define SOC_XT_WDT_SUPPORTED 1 - - -/*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_SUPPORTS_SECURE_DL_MODE 1 -#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 -#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 - +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1 /*-------------------------- AES CAPS -----------------------------------------*/ #define SOC_AES_SUPPORT_DMA (1) diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index 3c69d5360e..8ee3764fc7 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -5,6 +5,7 @@ #pragma once +/*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_CPU_CORES_NUM 1 #define SOC_DEDICATED_GPIO_SUPPORTED 1 #define SOC_GDMA_SUPPORTED 1 @@ -14,10 +15,9 @@ #define SOC_HMAC_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 - -/*-------------------------- COMMON CAPS ---------------------------------------*/ #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1 #define SOC_TEMP_SENSOR_SUPPORTED 1 diff --git a/components/soc/esp32s2/include/soc/soc_caps.h b/components/soc/esp32s2/include/soc/soc_caps.h index 620c5dc9ac..f9a07606d3 100644 --- a/components/soc/esp32s2/include/soc/soc_caps.h +++ b/components/soc/esp32s2/include/soc/soc_caps.h @@ -44,14 +44,15 @@ #define SOC_DIG_SIGN_SUPPORTED 1 #define SOC_HMAC_SUPPORTED 1 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 -#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 -#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 -#define SOC_TEMP_SENSOR_SUPPORTED 1 -#define SOC_CACHE_SUPPORT_WRAP 1 -#define SOC_FLASH_ENCRYPTION_XTS_AES 1 -#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 -#define SOC_PSRAM_DMA_CAPABLE 1 -#define SOC_XT_WDT_SUPPORTED 1 +#define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 +#define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 +#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED 1 +#define SOC_TEMP_SENSOR_SUPPORTED 1 +#define SOC_CACHE_SUPPORT_WRAP 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 +#define SOC_PSRAM_DMA_CAPABLE 1 +#define SOC_XT_WDT_SUPPORTED 1 /*-------------------------- ADC CAPS ----------------------------------------*/ /*!< SAR ADC Module*/ diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index ce26e3bade..29b9595ecb 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -31,11 +31,11 @@ #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 -#define SOC_SDMMC_HOST_SUPPORTED 1 +#define SOC_SDMMC_HOST_SUPPORTED 1 #define SOC_FLASH_ENCRYPTION_XTS_AES 1 -#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 -#define SOC_PSRAM_DMA_CAPABLE 1 -#define SOC_XT_WDT_SUPPORTED 1 +#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 +#define SOC_PSRAM_DMA_CAPABLE 1 +#define SOC_XT_WDT_SUPPORTED 1 /*-------------------------- SOC CAPS ----------------------------------------*/