2016-09-22 20:44:45 -04:00
|
|
|
menu "SPI Flash driver"
|
2023-01-30 05:03:41 -05:00
|
|
|
depends on !APP_BUILD_TYPE_PURE_RAM_APP
|
2016-09-22 20:44:45 -04:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
config SPI_FLASH_VERIFY_WRITE
|
|
|
|
|
bool "Verify SPI flash writes"
|
2023-03-02 03:10:02 -05:00
|
|
|
depends on !SPI_FLASH_ROM_IMPL
|
2019-01-25 11:10:53 -05:00
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If this option is enabled, any time SPI flash is written then the data will be read
|
|
|
|
|
back and verified. This can catch hardware problems with SPI flash, or flash which
|
|
|
|
|
was not erased before verification.
|
2017-10-06 00:38:01 -04:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
config SPI_FLASH_LOG_FAILED_WRITE
|
|
|
|
|
bool "Log errors if verification fails"
|
|
|
|
|
depends on SPI_FLASH_VERIFY_WRITE
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If this option is enabled, if SPI flash write verification fails then a log error line
|
|
|
|
|
will be written with the address, expected & actual values. This can be useful when
|
|
|
|
|
debugging hardware SPI flash problems.
|
2017-10-06 00:38:01 -04:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
config SPI_FLASH_WARN_SETTING_ZERO_TO_ONE
|
|
|
|
|
bool "Log warning if writing zero bits to ones"
|
|
|
|
|
depends on SPI_FLASH_VERIFY_WRITE
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
If this option is enabled, any SPI flash write which tries to set zero bits in the flash to
|
|
|
|
|
ones will log a warning. Such writes will not result in the requested data appearing identically
|
|
|
|
|
in flash once written, as SPI NOR flash can only set bits to one when an entire sector is erased.
|
|
|
|
|
After erasing, individual bits can only be written from one to zero.
|
2017-11-28 22:26:57 -05:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
Note that some software (such as SPIFFS) which is aware of SPI NOR flash may write one bits as an
|
|
|
|
|
optimisation, relying on the data in flash becoming a bitwise AND of the new data and any existing data.
|
|
|
|
|
Such software will log spurious warnings if this option is enabled.
|
2017-11-28 22:26:57 -05:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
config SPI_FLASH_ENABLE_COUNTERS
|
|
|
|
|
bool "Enable operation counters"
|
2022-08-23 00:31:53 -04:00
|
|
|
default n
|
2019-01-25 11:10:53 -05:00
|
|
|
help
|
|
|
|
|
This option enables the following APIs:
|
2016-09-22 20:44:45 -04:00
|
|
|
|
2022-08-23 00:31:53 -04:00
|
|
|
- esp_flash_reset_counters
|
|
|
|
|
- esp_flash_dump_counters
|
|
|
|
|
- esp_flash_get_counters
|
2017-03-09 02:29:00 -05:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
These APIs may be used to collect performance data for spi_flash APIs
|
|
|
|
|
and to help understand behaviour of libraries which use SPI flash.
|
2017-10-25 03:22:30 -04:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
config SPI_FLASH_ROM_DRIVER_PATCH
|
|
|
|
|
bool "Enable SPI flash ROM driver patched functions"
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Enable this flag to use patched versions of SPI flash ROM driver functions.
|
bootloader: fix the WRSR format for ISSI flash chips
1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability.
This commit helps to clear WEL when flash configuration is done.
**RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA.
2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips.
Status register bitmap of ISSI chip and GD chip:
| SR | ISSI | GD25LQ32C |
| -- | ---- | --------- |
| 0 | WIP | WIP |
| 1 | WEL | WEL |
| 2 | BP0 | BP0 |
| 3 | BP1 | BP1 |
| 4 | BP2 | BP2 |
| 5 | BP3 | BP3 |
| 6 | QE | BP4 |
| 7 | SRWD | SRP0 |
| 8 | | SRP1 |
| 9 | | QE |
| 10 | | SUS2 |
| 11 | | LB1 |
| 12 | | LB2 |
| 13 | | LB3 |
| 14 | | CMP |
| 15 | | SUS1 |
QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command.
However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips.
Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected.
This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6).
3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared.
This commit skips the clearing of status register if there is no protection bits active.
Also move the execute_flash_command to be a bootloader API; move
implementation of spi_flash_wrap_set to the bootloader
2020-03-12 06:20:31 -04:00
|
|
|
This option should be enabled, if any one of the following is true: (1) need to write
|
|
|
|
|
to flash on ESP32-D2WD; (2) main SPI flash is connected to non-default pins; (3) main
|
|
|
|
|
SPI flash chip is manufactured by ISSI.
|
2017-10-25 03:22:30 -04:00
|
|
|
|
2020-12-15 22:50:13 -05:00
|
|
|
config SPI_FLASH_ROM_IMPL
|
|
|
|
|
bool "Use esp_flash implementation in ROM"
|
2022-07-12 09:19:35 -04:00
|
|
|
depends on ESP_ROM_HAS_SPI_FLASH
|
2020-12-15 22:50:13 -05:00
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Enable this flag to use new SPI flash driver functions from ROM instead of ESP-IDF.
|
|
|
|
|
|
|
|
|
|
If keeping this as "n" in your project, you will have less free IRAM.
|
|
|
|
|
But you can use all of our flash features.
|
|
|
|
|
|
|
|
|
|
If making this as "y" in your project, you will increase free IRAM.
|
|
|
|
|
But you may miss out on some flash features and support for new flash chips.
|
|
|
|
|
|
2021-02-01 23:34:28 -05:00
|
|
|
Currently the ROM cannot support the following features:
|
|
|
|
|
|
|
|
|
|
- SPI_FLASH_AUTO_SUSPEND (C3, S3)
|
|
|
|
|
|
2019-06-11 04:45:26 -04:00
|
|
|
choice SPI_FLASH_DANGEROUS_WRITE
|
2019-01-25 11:10:53 -05:00
|
|
|
bool "Writing to dangerous flash regions"
|
2023-03-17 00:09:43 -04:00
|
|
|
default SPI_FLASH_DANGEROUS_WRITE_ALLOWED if APP_BUILD_TYPE_RAM
|
2019-06-11 04:45:26 -04:00
|
|
|
default SPI_FLASH_DANGEROUS_WRITE_ABORTS
|
2019-01-25 11:10:53 -05:00
|
|
|
help
|
|
|
|
|
SPI flash APIs can optionally abort or return a failure code
|
|
|
|
|
if erasing or writing addresses that fall at the beginning
|
|
|
|
|
of flash (covering the bootloader and partition table) or that
|
|
|
|
|
overlap the app partition that contains the running app.
|
2017-10-25 03:22:30 -04:00
|
|
|
|
2019-01-25 11:10:53 -05:00
|
|
|
It is not recommended to ever write to these regions from an IDF app,
|
|
|
|
|
and this check prevents logic errors or corrupted firmware memory from
|
|
|
|
|
damaging these regions.
|
|
|
|
|
|
|
|
|
|
Note that this feature *does not* check calls to the esp_rom_xxx SPI flash
|
|
|
|
|
ROM functions. These functions should not be called directly from IDF
|
|
|
|
|
applications.
|
|
|
|
|
|
2019-06-11 04:45:26 -04:00
|
|
|
config SPI_FLASH_DANGEROUS_WRITE_ABORTS
|
2019-06-11 04:32:59 -04:00
|
|
|
bool "Aborts"
|
2019-06-11 04:45:26 -04:00
|
|
|
config SPI_FLASH_DANGEROUS_WRITE_FAILS
|
2019-06-11 04:32:59 -04:00
|
|
|
bool "Fails"
|
2019-06-11 04:45:26 -04:00
|
|
|
config SPI_FLASH_DANGEROUS_WRITE_ALLOWED
|
2019-06-11 04:32:59 -04:00
|
|
|
bool "Allowed"
|
2019-01-25 11:10:53 -05:00
|
|
|
endchoice
|
2017-10-25 03:22:30 -04:00
|
|
|
|
2020-04-09 01:30:12 -04:00
|
|
|
config SPI_FLASH_SHARE_SPI1_BUS
|
|
|
|
|
bool "Support other devices attached to SPI1 bus"
|
|
|
|
|
default n
|
2023-04-14 04:24:32 -04:00
|
|
|
depends on IDF_TARGET_ESP32
|
|
|
|
|
select SPI_MASTER_ISR_IN_IRAM
|
2020-04-09 01:30:12 -04:00
|
|
|
help
|
|
|
|
|
Each SPI bus needs a lock for arbitration among devices. This allows multiple
|
|
|
|
|
devices on a same bus, but may reduce the speed of esp_flash driver access to the
|
|
|
|
|
main flash chip.
|
|
|
|
|
|
|
|
|
|
If you only need to use esp_flash driver to access the main flash chip, disable
|
|
|
|
|
this option, and the lock will be bypassed on SPI1 bus. Otherwise if extra devices
|
|
|
|
|
are needed to attach to SPI1 bus, enable this option.
|
|
|
|
|
|
2020-04-23 14:09:15 -04:00
|
|
|
config SPI_FLASH_BYPASS_BLOCK_ERASE
|
|
|
|
|
bool "Bypass a block erase and always do sector erase"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Some flash chips can have very high "max" erase times, especially for block erase (32KB or 64KB).
|
|
|
|
|
This option allows to bypass "block erase" and always do sector erase commands.
|
|
|
|
|
This will be much slower overall in most cases, but improves latency for other code to run.
|
|
|
|
|
|
2020-04-02 02:27:33 -04:00
|
|
|
config SPI_FLASH_YIELD_DURING_ERASE
|
|
|
|
|
bool "Enables yield operation during flash erase"
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
This allows to yield the CPUs between erase commands.
|
|
|
|
|
Prevents starvation of other tasks.
|
2021-12-20 04:24:13 -05:00
|
|
|
Please use this configuration together with ``SPI_FLASH_ERASE_YIELD_DURATION_MS`` and
|
|
|
|
|
``SPI_FLASH_ERASE_YIELD_TICKS`` after carefully checking flash datasheet to avoid a
|
|
|
|
|
watchdog timeout.
|
|
|
|
|
For more information, please check `SPI Flash API` reference documenation
|
|
|
|
|
under section `OS Function`.
|
2020-04-02 02:27:33 -04:00
|
|
|
|
|
|
|
|
config SPI_FLASH_ERASE_YIELD_DURATION_MS
|
|
|
|
|
int "Duration of erasing to yield CPUs (ms)"
|
|
|
|
|
depends on SPI_FLASH_YIELD_DURING_ERASE
|
|
|
|
|
default 20
|
|
|
|
|
help
|
|
|
|
|
If a duration of one erase command is large
|
|
|
|
|
then it will yield CPUs after finishing a current command.
|
|
|
|
|
|
|
|
|
|
config SPI_FLASH_ERASE_YIELD_TICKS
|
2020-04-24 16:12:43 -04:00
|
|
|
int "CPU release time (tick) for an erase operation"
|
2020-04-02 02:27:33 -04:00
|
|
|
depends on SPI_FLASH_YIELD_DURING_ERASE
|
|
|
|
|
default 1
|
|
|
|
|
help
|
|
|
|
|
Defines how many ticks will be before returning to continue a erasing.
|
|
|
|
|
|
2023-05-11 08:10:30 -04:00
|
|
|
config SPI_FLASH_SUSPEND_QVL_SUPPORTED
|
|
|
|
|
# Internally usage
|
|
|
|
|
bool
|
|
|
|
|
default y if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C2
|
|
|
|
|
default n
|
|
|
|
|
|
2020-12-17 23:57:55 -05:00
|
|
|
config SPI_FLASH_AUTO_SUSPEND
|
2021-03-19 05:39:56 -04:00
|
|
|
bool "Auto suspend long erase/write operations (READ DOCS FIRST)"
|
|
|
|
|
default n
|
2023-05-11 08:10:30 -04:00
|
|
|
depends on SPI_FLASH_SUSPEND_QVL_SUPPORTED && !SPI_FLASH_ROM_IMPL
|
2020-12-17 23:57:55 -05:00
|
|
|
help
|
2023-05-11 08:10:30 -04:00
|
|
|
This option is default n because it can't be used in every situation. You need to
|
|
|
|
|
evaluate this feature through suspend part in `SPI Flash API` document.
|
2021-02-01 23:34:28 -05:00
|
|
|
|
|
|
|
|
CAUTION: If you want to OTA to an app with this feature turned on, please make
|
|
|
|
|
sure the bootloader has the support for it. (later than IDF v4.3)
|
2020-12-17 23:57:55 -05:00
|
|
|
|
2023-05-11 08:10:30 -04:00
|
|
|
Auto-suspend feature only supported by specific flash chips.
|
2021-03-19 05:39:56 -04:00
|
|
|
If you are using an official module, please contact Espressif Business support.
|
|
|
|
|
Also reading auto suspend part in `SPI Flash API` document before you enable this function.
|
|
|
|
|
|
2020-06-04 05:21:34 -04:00
|
|
|
config SPI_FLASH_WRITE_CHUNK_SIZE
|
|
|
|
|
int "Flash write chunk size"
|
|
|
|
|
default 8192
|
|
|
|
|
range 256 8192
|
|
|
|
|
help
|
|
|
|
|
Flash write is broken down in terms of multiple (smaller) write operations.
|
|
|
|
|
This configuration options helps to set individual write chunk size, smaller
|
|
|
|
|
value here ensures that cache (and non-IRAM resident interrupts) remains
|
|
|
|
|
disabled for shorter duration.
|
|
|
|
|
|
2020-08-23 23:09:33 -04:00
|
|
|
config SPI_FLASH_SIZE_OVERRIDE
|
|
|
|
|
bool "Override flash size in bootloader header by ESPTOOLPY_FLASHSIZE"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
SPI Flash driver uses the flash size configured in bootloader header by default.
|
|
|
|
|
Enable this option to override flash size with latest ESPTOOLPY_FLASHSIZE value from
|
|
|
|
|
the app header if the size in the bootloader header is incorrect.
|
|
|
|
|
|
2020-08-24 04:57:21 -04:00
|
|
|
config SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED
|
|
|
|
|
bool "Flash timeout checkout disabled"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This option is helpful if you are using a flash chip whose timeout is quite large or unpredictable.
|
|
|
|
|
|
2021-02-28 23:56:34 -05:00
|
|
|
config SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST
|
|
|
|
|
bool "Override default chip driver list"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
This option allows the chip driver list to be customized, instead of using the default list provided by
|
|
|
|
|
ESP-IDF.
|
|
|
|
|
|
|
|
|
|
When this option is enabled, the default list is no longer compiled or linked. Instead, the
|
|
|
|
|
`default_registered_chips` structure must be provided by the user.
|
|
|
|
|
|
|
|
|
|
See example: custom_chip_driver under examples/storage for more details.
|
2020-08-24 04:57:21 -04:00
|
|
|
|
2022-05-30 04:49:19 -04:00
|
|
|
menu "SPI Flash behavior when brownout"
|
|
|
|
|
|
|
|
|
|
config SPI_FLASH_BROWNOUT_RESET_XMC
|
|
|
|
|
bool "Enable sending reset when brownout for XMC flash chips"
|
|
|
|
|
default y
|
|
|
|
|
select SPI_FLASH_BROWNOUT_RESET
|
|
|
|
|
help
|
|
|
|
|
When this option is selected, the patch will be enabled for XMC.
|
|
|
|
|
Follow the recommended flow by XMC for better stability.
|
|
|
|
|
|
|
|
|
|
DO NOT DISABLE UNLESS YOU KNOW WHAT YOU ARE DOING.
|
|
|
|
|
|
|
|
|
|
config SPI_FLASH_BROWNOUT_RESET
|
|
|
|
|
bool
|
|
|
|
|
default y
|
|
|
|
|
select ESP_SYSTEM_BROWNOUT_INTR
|
|
|
|
|
help
|
|
|
|
|
When brownout happens during flash erase/write operations,
|
|
|
|
|
send reset command to stop the flash operations to improve stability.
|
|
|
|
|
|
|
|
|
|
endmenu
|
|
|
|
|
|
2019-01-08 05:29:25 -05:00
|
|
|
menu "Auto-detect flash chips"
|
2021-02-28 23:56:34 -05:00
|
|
|
visible if !SPI_FLASH_OVERRIDE_CHIP_DRIVER_LIST
|
2019-01-08 05:29:25 -05:00
|
|
|
|
2023-02-06 06:23:10 -05:00
|
|
|
orsource "./$IDF_TARGET/Kconfig.soc_caps.in"
|
|
|
|
|
|
2019-01-08 05:29:25 -05:00
|
|
|
config SPI_FLASH_SUPPORT_ISSI_CHIP
|
|
|
|
|
bool "ISSI"
|
2023-02-06 06:23:10 -05:00
|
|
|
default y if SPI_FLASH_VENDOR_ISSI_SUPPORTED
|
|
|
|
|
default n
|
2019-01-08 05:29:25 -05:00
|
|
|
help
|
2019-09-09 12:56:46 -04:00
|
|
|
Enable this to support auto detection of ISSI chips if chip vendor not directly
|
|
|
|
|
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
|
|
|
|
chips, however will extend detecting time.
|
|
|
|
|
|
2020-03-19 10:49:25 -04:00
|
|
|
config SPI_FLASH_SUPPORT_MXIC_CHIP
|
|
|
|
|
bool "MXIC"
|
2023-02-06 06:23:10 -05:00
|
|
|
default y if SPI_FLASH_VENDOR_MXIC_SUPPORTED
|
|
|
|
|
default n
|
2020-03-19 10:49:25 -04:00
|
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|
help
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Enable this to support auto detection of MXIC chips if chip vendor not directly
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given by ``chip_drv`` member of the chip struct. This adds support for variant
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chips, however will extend detecting time.
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2019-09-09 12:56:46 -04:00
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config SPI_FLASH_SUPPORT_GD_CHIP
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bool "GigaDevice"
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2023-02-06 06:23:10 -05:00
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default y if SPI_FLASH_VENDOR_GD_SUPPORTED
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default n
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2019-09-09 12:56:46 -04:00
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help
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Enable this to support auto detection of GD (GigaDevice) chips if chip vendor not
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directly given by ``chip_drv`` member of the chip struct. If you are using Wrover
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modules, please don't disable this, otherwise your flash may not work in 4-bit
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mode.
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This adds support for variant chips, however will extend detecting time and image
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size. Note that the default chip driver supports the GD chips with product ID
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60H.
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2020-07-26 15:13:07 -04:00
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config SPI_FLASH_SUPPORT_WINBOND_CHIP
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bool "Winbond"
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2023-02-06 06:23:10 -05:00
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default y if SPI_FLASH_VENDOR_WINBOND_SUPPORTED
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default n
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2020-07-26 15:13:07 -04:00
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help
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Enable this to support auto detection of Winbond chips if chip vendor not directly
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given by ``chip_drv`` member of the chip struct. This adds support for variant
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chips, however will extend detecting time.
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2021-01-23 11:48:07 -05:00
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config SPI_FLASH_SUPPORT_BOYA_CHIP
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bool "BOYA"
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2021-12-01 02:13:02 -05:00
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# ESP32 doens't usually use this chip, default n to save iram.
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2023-02-06 06:23:10 -05:00
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default y if SPI_FLASH_VENDOR_BOYA_SUPPORTED
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default n
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2021-01-23 11:48:07 -05:00
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help
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Enable this to support auto detection of BOYA chips if chip vendor not directly
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given by ``chip_drv`` member of the chip struct. This adds support for variant
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chips, however will extend detecting time.
|
2021-12-01 02:13:02 -05:00
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config SPI_FLASH_SUPPORT_TH_CHIP
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bool "TH"
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# ESP32 doens't usually use this chip, default n to save iram.
|
2023-02-06 06:23:10 -05:00
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default y if SPI_FLASH_VENDOR_TH_SUPPORTED
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default n
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2021-12-01 02:13:02 -05:00
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help
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Enable this to support auto detection of TH chips if chip vendor not directly
|
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|
given by ``chip_drv`` member of the chip struct. This adds support for variant
|
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chips, however will extend detecting time.
|
2021-01-23 11:48:07 -05:00
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2021-09-01 03:58:15 -04:00
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config SPI_FLASH_SUPPORT_MXIC_OPI_CHIP
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bool "mxic (opi)"
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depends on IDF_TARGET_ESP32S3
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default y
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help
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Enable this to support auto detection of Octal MXIC chips if chip vendor not directly
|
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|
|
given by ``chip_drv`` member of the chip struct. This adds support for variant
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|
chips, however will extend detecting time.
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|
2019-01-08 05:29:25 -05:00
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endmenu #auto detect flash chips
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2021-01-22 05:14:27 -05:00
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config SPI_FLASH_ENABLE_ENCRYPTED_READ_WRITE
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|
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bool "Enable encrypted partition read/write operations"
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default y
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help
|
|
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|
|
This option enables flash read/write operations to encrypted partition/s. This option
|
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|
|
is kept enabled irrespective of state of flash encryption feature. However, in case
|
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|
|
application is not using flash encryption feature and is in need of some additional
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|
|
memory from IRAM region (~1KB) then this config can be disabled.
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|
2022-06-23 03:19:56 -04:00
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config SPI_FLASH_HPM_ENABLE
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bool
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default n
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help
|
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|
|
This option is invisible, and will be selected automatically
|
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|
|
when ``ESPTOOLPY_FLASHFREQ_120M`` is selected.
|
2023-04-13 23:37:09 -04:00
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config SPI_FLASH_32BIT_ADDRESS
|
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bool
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|
default y if ESPTOOLPY_FLASHSIZE_32MB || ESPTOOLPY_FLASHSIZE_64MB || ESPTOOLPY_FLASHSIZE_128MB
|
|
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|
|
default n
|
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help
|
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|
|
This is a helper config for 32bits address flash. Invisible for users.
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|
|
config SPI_FLASH_32BIT_ADDR_ENABLE
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|
|
bool "Enable 32-bit-address (over 16MB) SPI Flash access"
|
|
|
|
|
depends on SPI_FLASH_32BIT_ADDRESS && !ESPTOOLPY_OCT_FLASH && IDF_TARGET_ESP32S3 && IDF_EXPERIMENTAL_FEATURES
|
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|
default n
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|
help
|
|
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|
|
Enabling this option allows the CPU to access 32-bit-address flash beyond 16M range.
|
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|
|
1. This option only valid for 4-line flash. Octal flash doesn't need this.
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|
|
2. This option is experimental, which means it can't use on all flash chips stable, for more
|
|
|
|
|
information, please contact Espressif Business support.
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|
2016-09-22 20:44:45 -04:00
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endmenu
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