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esp-idf/components/driver/test/test_common_spi.c

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driver: update copyright notice
2021-05-23 19:06:17 -04:00
/*
* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
#include "test/test_common_spi.h"
#include "driver/spi_slave.h"
#include "esp_log.h"
global: move the soc component out of the common list This MR removes the common dependency from every IDF components to the SOC component. Currently, in the ``idf_functions.cmake`` script, we include the header path of SOC component by default for all components. But for better code organization (or maybe also benifits to the compiling speed), we may remove the dependency to SOC components for most components except the driver and kernel related components. In CMAKE, we have two kinds of header visibilities (set by include path visibility): (Assume component A --(depends on)--> B, B is the current component) 1. public (``COMPONENT_ADD_INCLUDEDIRS``): means this path is visible to other depending components (A) (visible to A and B) 2. private (``COMPONENT_PRIV_INCLUDEDIRS``): means this path is only visible to source files inside the component (visible to B only) and we have two kinds of depending ways: (Assume component A --(depends on)--> B --(depends on)--> C, B is the current component) 1. public (```COMPONENT_REQUIRES```): means B can access to public include path of C. All other components rely on you (A) will also be available for the public headers. (visible to A, B) 2. private (``COMPONENT_PRIV_REQUIRES``): means B can access to public include path of C, but don't propagate this relation to other components (A). (visible to B) 1. remove the common requirement in ``idf_functions.cmake``, this makes the SOC components invisible to all other components by default. 2. if a component (for example, DRIVER) really needs the dependency to SOC, add a private dependency to SOC for it. 3. some other components that don't really depends on the SOC may still meet some errors saying "can't find header soc/...", this is because it's depended component (DRIVER) incorrectly include the header of SOC in its public headers. Moving all this kind of #include into source files, or private headers 4. Fix the include requirements for some file which miss sufficient #include directives. (Previously they include some headers by the long long long header include link) This is a breaking change. Previous code may depends on the long include chain. You may need to include the following headers for some files after this commit: - soc/soc.h - soc/soc_memory_layout.h - driver/gpio.h - esp_sleep.h The major broken include chain includes: 1. esp_system.h no longer includes esp_sleep.h. The latter includes driver/gpio.h and driver/touch_pad.h. 2. ets_sys.h no longer includes soc/soc.h 3. freertos/portmacro.h no longer includes soc/soc_memory_layout.h some peripheral headers no longer includes their hw related headers, e.g. rom/gpio.h no longer includes soc/gpio_pins.h and soc/gpio_reg.h BREAKING CHANGE
2019-04-03 01:17:38 -04:00
#include "driver/gpio.h"
gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3 When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible to set pins 18 and 19 as GPIOs. This commit solves this by manually disabling USB JTAG when using pins 18 or 19. The functions shall use `gpio_hal_iomux_func_sel` instead of `PIN_FUNC_SELELECT`.
2021-03-15 22:55:05 -04:00
#include "hal/gpio_hal.h"
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
int test_freq_default[]=TEST_FREQ_DEFAULT();
const char MASTER_TAG[] = "test_master";
const char SLAVE_TAG[] = "test_slave";
DRAM_ATTR uint8_t spitest_master_send[] = {
0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43,
0x74,
0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43,
0x74,
0x93, 0x34, 0x56, 0x78, 0x9a, 0xbc, 0xde, 0xf0, 0xaa, 0xcc, 0xff, 0xee, 0x55, 0x77, 0x88, 0x43,
0x74,
};
DRAM_ATTR uint8_t spitest_slave_send[] = {
0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0,
0xda,
0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0,
0xda,
0xaa, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10, 0x13, 0x57, 0x9b, 0xdf, 0x24, 0x68, 0xac, 0xe0,
0xda,
};
void spitest_def_param(void* arg)
{
spitest_param_set_t *param_set=(spitest_param_set_t*)arg;
param_set->test_size = 8;
if (param_set->freq_list==NULL) param_set->freq_list = test_freq_default;
}
/**********************************************************************************
* functions for slave task
*********************************************************************************/
esp_err_t init_slave_context(spi_slave_task_context_t *context)
{
context->data_to_send = xQueueCreate( 16, sizeof( slave_txdata_t ));
if ( context->data_to_send == NULL ) {
return ESP_ERR_NO_MEM;
}
context->data_received = xRingbufferCreate( 1024, RINGBUF_TYPE_NOSPLIT );
if ( context->data_received == NULL ) {
return ESP_ERR_NO_MEM;
}
test: change spi test host to macros
2018-09-30 07:00:06 -04:00
context->spi=TEST_SLAVE_HOST;
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
return ESP_OK;
}
void deinit_slave_context(spi_slave_task_context_t *context)
{
TEST_ASSERT( context->data_to_send != NULL );
vQueueDelete( context->data_to_send );
context->data_to_send = NULL;
TEST_ASSERT( context->data_received != NULL );
vRingbufferDelete( context->data_received );
context->data_received = NULL;
}
/* The task requires a queue and a ringbuf, which should be initialized before task starts.
Send ``slave_txdata_t`` to the queue to make the task send data;
the task returns data got to the ringbuf, which should have sufficient size.
*/
void spitest_slave_task(void* arg)
{
spi_slave_task_context_t* context = (spi_slave_task_context_t*) arg;
QueueHandle_t queue = context->data_to_send;
RingbufHandle_t ringbuf = context->data_received;
uint8_t recvbuf[320+8];
slave_txdata_t txdata;
ESP_LOGI( SLAVE_TAG, "slave up" );
//never quit, but blocked by the queue, waiting to be killed, when no more send from main task.
while( 1 ) {
BaseType_t ret = xQueueReceive( queue, &txdata, portMAX_DELAY );
assert(ret);
spi_slave_transaction_t t = {};
t.length = txdata.len;
t.tx_buffer = txdata.start;
t.rx_buffer = recvbuf+8;
//loop until trans_len != 0 to skip glitches
do {
TEST_ESP_OK( spi_slave_transmit( context->spi, &t, portMAX_DELAY ) );
} while ( t.trans_len <= 2 );
memcpy(recvbuf, &t.trans_len, sizeof(uint32_t));
*(uint8_t**)(recvbuf+4) = (uint8_t*)txdata.start;
spi: re-enable the unit tests for esp32s2beta
2019-10-11 04:07:43 -04:00
ESP_LOGD( SLAVE_TAG, "received: %d", t.trans_len );
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
xRingbufferSend( ringbuf, recvbuf, 8+(t.trans_len+7)/8, portMAX_DELAY );
}
}
void slave_pull_up(const spi_bus_config_t* cfg, int spics_io_num)
{
gpio_set_pull_mode(cfg->mosi_io_num, GPIO_PULLUP_ONLY);
gpio_set_pull_mode(cfg->sclk_io_num, GPIO_PULLUP_ONLY);
gpio_set_pull_mode(spics_io_num, GPIO_PULLUP_ONLY);
}
/**********************************************************************************
* functions for slave task
*********************************************************************************/
static int test_len[] = {1, 3, 5, 7, 9, 11, 33, 64};
void spitest_init_transactions(const spitest_param_set_t *cfg, spitest_context_t* context)
{
spi_transaction_t* trans = context->master_trans;
uint8_t *rx_buf_ptr = context->master_rxbuf;
const spi_dup_t dup = cfg->dup;
for (int i = 0; i < cfg->test_size; i++) {
const void* tx_buffer = spitest_master_send + i%8;
int length = 8*test_len[i];
if (cfg->length_aligned) length = (length+31)&(~31);
if (dup == HALF_DUPLEX_MISO) {
trans[i] = (spi_transaction_t) {
.rx_buffer = rx_buf_ptr,
.rxlength = length,
};
} else if (dup == HALF_DUPLEX_MOSI) {
trans[i] = (spi_transaction_t) {
.tx_buffer = tx_buffer,
.length = length,
};
} else {
trans[i] = (spi_transaction_t) {
.tx_buffer = tx_buffer,
.length = length,
.rx_buffer = rx_buf_ptr,
};
}
rx_buf_ptr = (uint8_t*)( (uint32_t)(rx_buf_ptr + (length+7)/8 + 3) & (~3));
const void* slave_tx = spitest_slave_send + (cfg->slave_unaligned_addr? i%3: (i%3)*4);
//prepare slave tx data
context->slave_trans[i] = (slave_txdata_t) {
.start = slave_tx,
.len = 512,
};
if (cfg->slave_dma_chan != 0) context->slave_trans[i].len = 1024;
}
}
void spitest_master_print_data(spi_transaction_t *t, int rxlength)
{
if (t->tx_buffer) ESP_LOG_BUFFER_HEX( "master tx", t->tx_buffer, t->length/8 );
if (t->rx_buffer) ESP_LOG_BUFFER_HEX( "master rx", t->rx_buffer, rxlength/8 );
}
void spitest_slave_print_data(slave_rxdata_t *t, bool print_rxdata)
{
int rcv_len = (t->len+7)/8;
ESP_LOGI(SLAVE_TAG, "trans_len: %d", t->len);
ESP_LOG_BUFFER_HEX("slave tx", t->tx_start, rcv_len);
if (print_rxdata) ESP_LOG_BUFFER_HEX("slave rx", t->data, rcv_len);
}
esp_err_t spitest_check_data(int len, spi_transaction_t *master_t, slave_rxdata_t *slave_t, bool check_master_data, bool check_slave_len, bool check_slave_data)
{
spi: re-enable the unit tests for esp32s2beta
2019-10-11 04:07:43 -04:00
esp_err_t ret = ESP_OK;
uint32_t rcv_len = slave_t->len;
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
//currently the rcv_len can be in range of [t->length-1, t->length+3]
spi: re-enable the unit tests for esp32s2beta
2019-10-11 04:07:43 -04:00
if (check_slave_len &&
(rcv_len < len - 1 || rcv_len > len + 4)) {
ret = ESP_FAIL;
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
}
spi: re-enable the unit tests for esp32s2beta
2019-10-11 04:07:43 -04:00
if (check_master_data &&
memcmp(slave_t->tx_start, master_t->rx_buffer, (len + 7) / 8) != 0 ) {
ret = ESP_FAIL;
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
}
spi: re-enable the unit tests for esp32s2beta
2019-10-11 04:07:43 -04:00
if (check_slave_data &&
memcmp(master_t->tx_buffer, slave_t->data, (len + 7) / 8) != 0 ) {
ret = ESP_FAIL;
}
if (ret != ESP_OK) {
ESP_LOGI(SLAVE_TAG, "slave_recv_len: %d", rcv_len);
spitest_master_print_data(master_t, len);
spitest_slave_print_data(slave_t, true);
//already failed, try to use the TEST_ASSERT to output the reason...
if (check_slave_len) {
TEST_ASSERT(rcv_len >= len - 1 && rcv_len <= len + 4);
}
TEST_ASSERT_EQUAL_HEX8_ARRAY(slave_t->tx_start, master_t->rx_buffer, (len + 7) / 8);
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
TEST_ASSERT_EQUAL_HEX8_ARRAY(master_t->tx_buffer, slave_t->data, (len + 7) / 8);
}
spi: re-enable the unit tests for esp32s2beta
2019-10-11 04:07:43 -04:00
spi: add new test for timing and mode New unit tests added ------------------------ **Local:** Local test uses the GPIO matrix to connect the master and the slave on the same board. When the master needs the iomux, the master uses the GPIOs of its own, the slave connect to the pins by GPIO matrix; When the slave needs the iomux, the slave uses the GPIOs of its own, the master connects to the pins by GPIO matrix. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. **M & S**: Master & slave tests performs the test with two boards. The master and slave use iomux or gpio matrix according to the config. - Provide a new unit test which performs freq scanning in mode 0. It scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum frequency allowed. - Provide a new unit test which performs mode test with significant frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum frequency allowed.
2018-09-21 04:48:04 -04:00
return ESP_OK;
}
void master_free_device_bus(spi_device_handle_t spi)
{
TEST_ESP_OK( spi_bus_remove_device(spi) );
TEST_ESP_OK( spi_bus_free(TEST_SPI_HOST) );
}
void spitest_gpio_output_sel(uint32_t gpio_num, int func, uint32_t signal_idx)
{
gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3 When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible to set pins 18 and 19 as GPIOs. This commit solves this by manually disabling USB JTAG when using pins 18 or 19. The functions shall use `gpio_hal_iomux_func_sel` instead of `PIN_FUNC_SELELECT`.
2021-03-15 22:55:05 -04:00
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
spi_master: add a test for HD master to receive data correctly via dma Issue Description: If master is in HD mode, if it sends data without receiving data, it will still enable the RX DMA because of old version ESP32 silicon issue. And because there is no correctly linked RX DMA descriptor, an inlink_dscr_error intr will be seen, which will influence the following RX transactions. This issue is only found on ESP32.
2020-11-30 08:21:43 -05:00
GPIO.func_out_sel_cfg[gpio_num].func_sel = signal_idx;
}
void spitest_gpio_input_sel(uint32_t gpio_num, int func, uint32_t signal_idx)
{
gpio: Disable USB JTAG when setting pins 18 and 19 as GPIOs on ESP32C3 When `DIS_USB_JTAG` eFuse is NOT burned (`False`), it is not possible to set pins 18 and 19 as GPIOs. This commit solves this by manually disabling USB JTAG when using pins 18 or 19. The functions shall use `gpio_hal_iomux_func_sel` instead of `PIN_FUNC_SELELECT`.
2021-03-15 22:55:05 -04:00
gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], func);
spi_master: add a test for HD master to receive data correctly via dma Issue Description: If master is in HD mode, if it sends data without receiving data, it will still enable the RX DMA because of old version ESP32 silicon issue. And because there is no correctly linked RX DMA descriptor, an inlink_dscr_error intr will be seen, which will influence the following RX transactions. This issue is only found on ESP32.
2020-11-30 08:21:43 -05:00
GPIO.func_in_sel_cfg[signal_idx].func_sel = gpio_num;
}
//Note this cs_num is the ID of the connected devices' ID, e.g. if 2 devices are connected to the bus,
//then the cs_num of the 1st and 2nd devices are 0 and 1 respectively.
void same_pin_func_sel(spi_bus_config_t bus, spi_device_interface_config_t dev, uint8_t cs_num)
{
spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in);
spitest_gpio_output_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiq_in);
spitest_gpio_output_sel(dev.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spics_out[cs_num]);
spitest_gpio_input_sel(dev.spics_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spics_in);
spitest_gpio_output_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spiclk_out);
spitest_gpio_input_sel(bus.sclk_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiclk_in);
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
GPIO.func_in_sel_cfg[FSPIQ_IN_IDX].sig_in_sel = 1;
#endif
Whitespace: Automated whitespace fixes (large commit) Apply the pre-commit hook whitespace fixes to all files in the repo. (Line endings, blank lines at end of file, trailing whitespace)
2020-11-10 02:40:01 -05:00
}
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