2022-08-19 08:37:46 -04:00
|
|
|
/*
|
|
|
|
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
|
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
|
|
*/
|
2019-09-25 12:22:36 -04:00
|
|
|
|
|
|
|
#include "soc/interrupts.h"
|
|
|
|
|
|
|
|
const char * const esp_isr_names[ETS_MAX_INTR_SOURCE] = {
|
|
|
|
[0] = "WIFI_MAC",
|
|
|
|
[1] = "WIFI_NMI",
|
|
|
|
[2] = "WIFI_PWR",
|
|
|
|
[3] = "WIFI_BB",
|
|
|
|
[4] = "BT_MAC",
|
|
|
|
[5] = "BT_BB",
|
|
|
|
[6] = "BT_BB_NMI",
|
|
|
|
[7] = "RWBT",
|
|
|
|
[8] = "RWBLE",
|
|
|
|
[9] = "RWBT_NMI",
|
|
|
|
[10] = "RWBLE_NMI",
|
|
|
|
[11] = "SLC0",
|
|
|
|
[12] = "SLC1",
|
|
|
|
[13] = "UHCI0",
|
|
|
|
[14] = "UHCI1",
|
|
|
|
[15] = "TG0_T0_LEVEL",
|
|
|
|
[16] = "TG0_T1_LEVEL",
|
|
|
|
[17] = "TG0_WDT_LEVEL",
|
|
|
|
[18] = "TG0_LACT_LEVEL",
|
|
|
|
[19] = "TG1_T0_LEVEL",
|
|
|
|
[20] = "TG1_T1_LEVEL",
|
|
|
|
[21] = "TG1_WDT_LEVEL",
|
|
|
|
[22] = "TG1_LACT_LEVEL",
|
|
|
|
[23] = "GPIO",
|
|
|
|
[24] = "GPIO_NMI",
|
|
|
|
[25] = "GPIO_INTR_2",
|
|
|
|
[26] = "GPIO_NMI_2",
|
|
|
|
[27] = "DEDICATED_GPIO",
|
|
|
|
[28] = "FROM_CPU_INTR0",
|
|
|
|
[29] = "FROM_CPU_INTR1",
|
|
|
|
[30] = "FROM_CPU_INTR2",
|
|
|
|
[31] = "FROM_CPU_INTR3",
|
|
|
|
[32] = "SPI1",
|
|
|
|
[33] = "SPI2",
|
|
|
|
[34] = "SPI3",
|
|
|
|
[35] = "I2S0",
|
|
|
|
[36] = "I2S1",
|
|
|
|
[37] = "UART0",
|
|
|
|
[38] = "UART1",
|
|
|
|
[39] = "UART2",
|
|
|
|
[40] = "SDIO_HOST",
|
|
|
|
[41] = "PWM0",
|
|
|
|
[42] = "PWM1",
|
|
|
|
[43] = "PWM2",
|
|
|
|
[44] = "PWM3",
|
|
|
|
[45] = "LEDC",
|
|
|
|
[46] = "EFUSE",
|
2022-08-19 08:37:46 -04:00
|
|
|
[47] = "TWAI",
|
2019-09-25 12:22:36 -04:00
|
|
|
[48] = "USB",
|
|
|
|
[49] = "RTC_CORE",
|
|
|
|
[50] = "RMT",
|
|
|
|
[51] = "PCNT",
|
|
|
|
[52] = "I2C_EXT0",
|
|
|
|
[53] = "I2C_EXT1",
|
|
|
|
[54] = "RSA",
|
2020-01-22 07:39:42 -05:00
|
|
|
[55] = "SHA",
|
|
|
|
[56] = "AES",
|
|
|
|
[57] = "SPI2_DMA",
|
|
|
|
[58] = "SPI3_DMA",
|
|
|
|
[59] = "WDT",
|
|
|
|
[60] = "TIMER1",
|
|
|
|
[61] = "TIMER2",
|
|
|
|
[62] = "TG0_T0_EDGE",
|
|
|
|
[63] = "TG0_T1_EDGE",
|
|
|
|
[64] = "TG0_WDT_EDGE",
|
|
|
|
[65] = "TG0_LACT_EDGE",
|
|
|
|
[66] = "TG1_T0_EDGE",
|
|
|
|
[67] = "TG1_T1_EDGE",
|
|
|
|
[68] = "TG1_WDT_EDGE",
|
|
|
|
[69] = "TG1_LACT_EDGE",
|
|
|
|
[70] = "CACHE_IA",
|
|
|
|
[71] = "SYSTIMER_TARGET0",
|
|
|
|
[72] = "SYSTIMER_TARGET1",
|
|
|
|
[73] = "SYSTIMER_TARGET2",
|
|
|
|
[74] = "ASSIST_DEBUG",
|
|
|
|
[75] = "PMS_PRO_IRAM0_ILG",
|
|
|
|
[76] = "PMS_PRO_DRAM0_ILG",
|
|
|
|
[77] = "PMS_PRO_DPORT_ILG",
|
|
|
|
[78] = "PMS_PRO_AHB_ILG",
|
|
|
|
[79] = "PMS_PRO_CACHE_ILG",
|
|
|
|
[80] = "PMS_DMA_APB_I_ILG",
|
|
|
|
[81] = "PMS_DMA_RX_I_ILG",
|
|
|
|
[82] = "PMS_DMA_TX_I_ILG",
|
|
|
|
[83] = "SPI0_REJECT_CACHE",
|
2019-09-25 12:22:36 -04:00
|
|
|
[84] = "DMA_COPY",
|
|
|
|
[85] = "SPI4_DMA",
|
|
|
|
[86] = "SPI4",
|
2020-01-22 07:39:42 -05:00
|
|
|
[87] = "ICACHE_PRELOAD",
|
|
|
|
[88] = "DCACHE_PRELOAD",
|
|
|
|
[89] = "APB_ADC",
|
|
|
|
[90] = "CRYPTO_DMA",
|
|
|
|
[91] = "CPU_PERI_ERR",
|
|
|
|
[92] = "APB_PERI_ERR",
|
|
|
|
[93] = "DCACHE_SYNC",
|
|
|
|
[94] = "ICACHE_SYNC",
|
2019-09-25 12:22:36 -04:00
|
|
|
};
|