uint32_treg_vdd_spi_modecurlim:1;/*SPI regulator switches current limit mode.*/
uint32_treg_vdd_spi_drefh:2;/*SPI regulator high voltage reference.*/
};
uint32_tval;
}rd_repeat_data0;
union{
struct{
uint32_treg_vdd_spi_drefm:2;/*SPI regulator medium voltage reference.*/
uint32_treg_vdd_spi_drefl:2;/*SPI regulator low voltage reference.*/
uint32_treg_vdd_spi_xpd:1;/*SPI regulator power up signal.*/
uint32_treg_vdd_spi_tieh:1;/*SPI regulator output is short connected to VDD3P3_RTC_IO.*/
uint32_treg_vdd_spi_force:1;/*Set this bit and force to use the configuration of eFuse to configure VDD_SPI.*/
uint32_treg_vdd_spi_en_init:1;/*Set SPI regulator to 0 to configure init[1:0]=0.*/
uint32_treg_vdd_spi_encurlim:1;/*Set SPI regulator to 1 to enable output current limit.*/
uint32_treg_vdd_spi_dcurlim:3;/*Tunes the current limit threshold of SPI regulator when tieh=0, about 800 mA/(8+d).*/
uint32_treg_vdd_spi_init:2;/*Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K 3: 2 K.*/
uint32_treg_vdd_spi_dcap:2;/*Prevents SPI regulator from overshoot.*/
uint32_treg_wdt_delay_sel:2;/*Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.*/
uint32_treg_spi_boot_crypt_cnt:3;/*Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.*/
uint32_treg_secure_boot_key_revoke0:1;/*Set this bit to enable revoking first secure boot key.*/
uint32_treg_secure_boot_key_revoke1:1;/*Set this bit to enable revoking second secure boot key.*/
uint32_treg_secure_boot_key_revoke2:1;/*Set this bit to enable revoking third secure boot key.*/
uint32_treg_key_purpose_0:4;/*Purpose of Key0.*/
uint32_treg_key_purpose_1:4;/*Purpose of Key1.*/
};
uint32_tval;
}rd_repeat_data1;
union{
struct{
uint32_treg_key_purpose_2:4;/*Purpose of Key2.*/
uint32_treg_key_purpose_3:4;/*Purpose of Key3.*/
uint32_treg_key_purpose_4:4;/*Purpose of Key4.*/
uint32_treg_key_purpose_5:4;/*Purpose of Key5.*/
uint32_treg_rpt4_reserved0:4;/*Reserved (used for four backups method).*/
uint32_treg_secure_boot_en:1;/*Set this bit to enable secure boot.*/
uint32_treg_secure_boot_aggressive_revoke:1;/*Set this bit to enable revoking aggressive secure boot.*/
uint32_treg_dis_usb_jtag:1;/*Set this bit to disable function of usb switch to jtag in module of usb device.*/
uint32_treg_dis_usb_device:1;/*Set this bit to disable usb device.*/
uint32_treg_strap_jtag_sel:1;/*Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.*/
uint32_treg_usb_phy_sel:1;/*This bit is used to switch internal PHY and external PHY for USB OTG and USB Device. 0: internal PHY is assigned to USB Device while external PHY is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while external PHY is assigned to USB Device.*/
uint32_treg_power_glitch_dsense:2;/*Sample delay configuration of power glitch.*/
uint32_treg_flash_tpuw:4;/*Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.*/
};
uint32_tval;
}rd_repeat_data2;
union{
struct{
uint32_treg_dis_download_mode:1;/*Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).*/
uint32_treg_dis_legacy_spi_boot:1;/*Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).*/
uint32_treg_uart_print_channel:1;/*Selectes the default UART print channel. 0: UART0. 1: UART1.*/
uint32_treg_flash_ecc_mode:1;/*Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.*/
uint32_treg_dis_usb_download_mode:1;/*Set this bit to disable UART download mode through USB.*/
uint32_treg_enable_security_download:1;/*Set this bit to enable secure UART download mode.*/
uint32_treg_uart_print_control:2;/*Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.*/
uint32_treg_pin_power_selection:1;/*GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.*/
uint32_treg_flash_type:1;/*Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.*/
uint32_trd_mac_spi_8m_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_mac_spi_8m_fail:1;/*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_trd_sys_part1_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_sys_part1_fail:1;/*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_trd_usr_data_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_usr_data_fail:1;/*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_trd_key0_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_key0_fail:1;/*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
uint32_trd_key1_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_key1_fail:1;/*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
uint32_trd_key2_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_key2_fail:1;/*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
uint32_trd_key3_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_key3_fail:1;/*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
uint32_trd_key4_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_key4_fail:1;/*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
};
uint32_tval;
}rd_rs_err0;
union{
struct{
uint32_trd_key5_err_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_key5_fail:1;/*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_trd_sys_part2_num:3;/*The value of this signal means the number of error bytes.*/
uint32_trd_sys_part2_fail:1;/*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
uint32_treserved8:24;/*Reserved.*/
};
uint32_tval;
}rd_rs_err1;
union{
struct{
uint32_tmem_force_pd:1;/*Set this bit to force eFuse SRAM into power-saving mode.*/
uint32_tmem_clk_force_on:1;/*Set this bit and force to activate clock signal of eFuse SRAM.*/
uint32_tmem_force_pu:1;/*Set this bit to force eFuse SRAM into working mode.*/
uint32_treserved3:13;/*Reserved.*/
uint32_tclk_en:1;/*Set this bit and force to enable clock signal of eFuse memory.*/
