2017-07-20 04:26:35 -04:00
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/*
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Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
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*/
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// Copyright 2013-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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2017-11-03 03:10:47 -04:00
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#include "esp_log.h"
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2017-07-20 04:26:35 -04:00
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#include "spiram_psram.h"
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#include "rom/ets_sys.h"
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#include "rom/spi_flash.h"
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#include "rom/gpio.h"
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#include "rom/cache.h"
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2019-05-07 04:36:37 -04:00
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#include "rom/efuse.h"
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2017-07-20 04:26:35 -04:00
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_sig_map.h"
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2017-11-03 03:10:47 -04:00
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#include "soc/efuse_reg.h"
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2017-07-20 04:26:35 -04:00
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#include "driver/gpio.h"
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#include "driver/spi_common.h"
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2017-12-19 06:12:58 -05:00
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#include "driver/periph_ctrl.h"
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2019-05-07 04:36:37 -04:00
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#include "bootloader_common.h"
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2017-07-20 04:26:35 -04:00
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#if CONFIG_SPIRAM_SUPPORT
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2018-04-20 04:59:25 -04:00
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#include "soc/rtc.h"
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2017-07-20 04:26:35 -04:00
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//Commands for PSRAM chip
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2018-07-03 23:43:30 -04:00
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ_DUMMY 0x3
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#define PSRAM_FAST_READ_QUAD 0xEB
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#define PSRAM_FAST_READ_QUAD_DUMMY 0x5
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#define PSRAM_WRITE 0x02
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#define PSRAM_QUAD_WRITE 0x38
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#define PSRAM_ENTER_QMODE 0x35
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#define PSRAM_EXIT_QMODE 0xF5
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#define PSRAM_RESET_EN 0x66
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#define PSRAM_RESET 0x99
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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typedef enum {
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PSRAM_CLK_MODE_NORM = 0, /*!< Normal SPI mode */
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PSRAM_CLK_MODE_DCLK = 1, /*!< Two extra clock cycles after CS is set high level */
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} psram_clk_mode_t;
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#define PSRAM_ID_KGD_M 0xff
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#define PSRAM_ID_KGD_S 8
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#define PSRAM_ID_KGD 0x5d
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#define PSRAM_ID_EID_M 0xff
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#define PSRAM_ID_EID_S 16
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2018-11-20 07:39:47 -05:00
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// Use the [7:5](bit7~bit5) of EID to distinguish the psram size:
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//
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// BIT7 | BIT6 | BIT5 | SIZE(MBIT)
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// -------------------------------------
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// 0 | 0 | 0 | 16
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// 0 | 0 | 1 | 32
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// 0 | 1 | 0 | 64
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#define PSRAM_EID_SIZE_M 0x07
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#define PSRAM_EID_SIZE_S 5
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typedef enum {
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PSRAM_EID_SIZE_16MBITS = 0,
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PSRAM_EID_SIZE_32MBITS = 1,
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PSRAM_EID_SIZE_64MBITS = 2,
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} psram_eid_size_t;
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2018-09-27 05:00:48 -04:00
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2018-11-20 07:39:47 -05:00
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#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M)
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#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M)
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#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M)
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#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD)
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// For the old version 32Mbit psram, using the spicial driver */
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#define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20)
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#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26)
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2017-07-20 04:26:35 -04:00
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2018-12-25 08:15:15 -05:00
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// IO-pins for PSRAM.
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2017-07-20 04:26:35 -04:00
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// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
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// hardcode the flash pins as well, making this code incompatible with either a setup
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// that has the flash on non-standard pins or ESP32s with built-in flash.
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2019-05-07 04:36:37 -04:00
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#define FLASH_CLK_IO 6
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2018-11-20 07:39:47 -05:00
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#define FLASH_CS_IO 11
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2019-05-07 04:36:37 -04:00
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#define PSRAM_SPIQ_SD0_IO 7
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#define PSRAM_SPID_SD1_IO 8
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2018-11-20 07:39:47 -05:00
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#define PSRAM_SPIWP_SD3_IO 10
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2019-05-07 04:36:37 -04:00
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#define PSRAM_SPIHD_SD2_IO 9
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#define FLASH_HSPI_CLK_IO 14
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#define FLASH_HSPI_CS_IO 15
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#define PSRAM_HSPI_SPIQ_SD0_IO 12
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#define PSRAM_HSPI_SPID_SD1_IO 13
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#define PSRAM_HSPI_SPIWP_SD3_IO 2
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#define PSRAM_HSPI_SPIHD_SD2_IO 4
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// PSRAM clock and cs IO should be configured based on hardware design.
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// For ESP32-WROVER or ESP32-WROVER-B module, the clock IO is IO17, the cs IO is IO16,
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// they are the default value for these two configs.
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#define D0WD_PSRAM_CLK_IO CONFIG_D0WD_PSRAM_CLK_IO // Default value is 17
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#define D0WD_PSRAM_CS_IO CONFIG_D0WD_PSRAM_CS_IO // Default value is 16
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#define D2WD_PSRAM_CLK_IO CONFIG_D2WD_PSRAM_CLK_IO // Default value is 9
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#define D2WD_PSRAM_CS_IO CONFIG_D2WD_PSRAM_CS_IO // Default value is 10
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// For ESP32-PICO chip, the psram share clock with flash. The flash clock pin is fixed, which is IO6.
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#define PICO_PSRAM_CLK_IO 6
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#define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO // Default value is 10
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typedef struct {
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uint8_t flash_clk_io;
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uint8_t flash_cs_io;
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uint8_t psram_clk_io;
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uint8_t psram_cs_io;
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uint8_t psram_spiq_sd0_io;
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uint8_t psram_spid_sd1_io;
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uint8_t psram_spiwp_sd3_io;
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uint8_t psram_spihd_sd2_io;
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} psram_io_t;
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2017-11-03 03:10:47 -04:00
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#define PSRAM_INTERNAL_IO_28 28
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#define PSRAM_INTERNAL_IO_29 29
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2017-07-20 04:26:35 -04:00
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#define PSRAM_IO_MATRIX_DUMMY_40M 1
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#define PSRAM_IO_MATRIX_DUMMY_80M 2
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2018-11-20 07:39:47 -05:00
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#define _SPI_CACHE_PORT 0
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#define _SPI_FLASH_PORT 1
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#define _SPI_80M_CLK_DIV 1
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#define _SPI_40M_CLK_DIV 2
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2019-02-13 03:06:10 -05:00
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//For 4MB PSRAM, we need one more SPI host, select which one to use by kconfig
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#ifdef CONFIG_SPIRAM_OCCUPY_HSPI_HOST
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#define PSRAM_SPI_MODULE PERIPH_HSPI_MODULE
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#define PSRAM_SPI_HOST HSPI_HOST
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#define PSRAM_CLK_SIGNAL HSPICLK_OUT_IDX
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#define PSRAM_SPI_NUM PSRAM_SPI_2
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#define PSRAM_SPICLKEN DPORT_SPI2_CLK_EN
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#elif defined CONFIG_SPIRAM_OCCUPY_VSPI_HOST
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#define PSRAM_SPI_MODULE PERIPH_VSPI_MODULE
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#define PSRAM_SPI_HOST VSPI_HOST
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#define PSRAM_CLK_SIGNAL VSPICLK_OUT_IDX
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#define PSRAM_SPI_NUM PSRAM_SPI_3
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#define PSRAM_SPICLKEN DPORT_SPI3_CLK_EN
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#else //set to SPI avoid HSPI and VSPI being used
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#define PSRAM_SPI_MODULE PERIPH_SPI_MODULE
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#define PSRAM_SPI_HOST SPI_HOST
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#define PSRAM_CLK_SIGNAL SPICLK_OUT_IDX
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#define PSRAM_SPI_NUM PSRAM_SPI_1
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#define PSRAM_SPICLKEN DPORT_SPI01_CLK_EN
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#endif
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2017-11-03 03:10:47 -04:00
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static const char* TAG = "psram";
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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PSRAM_SPI_2,
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PSRAM_SPI_3,
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PSRAM_SPI_MAX ,
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} psram_spi_num_t;
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static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
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2018-07-03 23:43:30 -04:00
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static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK;
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static uint32_t s_psram_id = 0;
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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static int extra_dummy = 0;
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typedef enum {
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PSRAM_CMD_QPI,
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PSRAM_CMD_SPI,
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} psram_cmd_mode_t;
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typedef struct {
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uint16_t cmd; /*!< Command value */
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uint16_t cmdBitLen; /*!< Command byte length*/
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uint32_t *addr; /*!< Point to address value*/
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uint16_t addrBitLen; /*!< Address byte length*/
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uint32_t *txData; /*!< Point to send data buffer*/
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uint16_t txDataBitLen; /*!< Send data byte length.*/
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uint32_t *rxData; /*!< Point to recevie data buffer*/
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uint16_t rxDataBitLen; /*!< Recevie Data byte length.*/
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uint32_t dummyBitLen;
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} psram_cmd_t;
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
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static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
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{
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int i;
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for (i = 0; i < 16; i++) {
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WRITE_PERI_REG(SPI_W0_REG(spi_num)+i*4, 0);
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}
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}
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//set basic SPI write mode
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static void psram_set_basic_write_mode(psram_spi_num_t spi_num)
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{
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
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}
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//set QPI write mode
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static void psram_set_qio_write_mode(psram_spi_num_t spi_num)
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{
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
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}
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//set QPI read mode
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static void psram_set_qio_read_mode(psram_spi_num_t spi_num)
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{
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SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
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}
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//set SPI read mode
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static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
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{
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
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}
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//start sending cmd/addr and optionally, receiving data
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static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t* pRxData, uint16_t rxByteLen,
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psram_cmd_mode_t cmd_mode)
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{
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//get cs1
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
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uint32_t mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf;
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uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M);
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if (cmd_mode == PSRAM_CMD_SPI) {
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psram_set_basic_write_mode(spi_num);
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psram_set_basic_read_mode(spi_num);
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} else if (cmd_mode == PSRAM_CMD_QPI) {
|
|
|
|
|
psram_set_qio_write_mode(spi_num);
|
|
|
|
|
psram_set_qio_read_mode(spi_num);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//Wait for SPI0 to idle
|
|
|
|
|
while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
|
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
|
|
|
|
|
|
|
|
|
|
// Start send data
|
|
|
|
|
SET_PERI_REG_MASK(SPI_CMD_REG(spi_num), SPI_USR);
|
|
|
|
|
while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR));
|
|
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
|
|
|
|
|
|
|
|
|
|
//recover spi mode
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER_REG(spi_num), (pRxData?SPI_FWRITE_DUAL_M:0xf), mode_backup, SPI_FWRITE_DUAL_S);
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
|
|
|
|
|
SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), rd_mode_backup);
|
|
|
|
|
|
|
|
|
|
//return cs to cs0
|
|
|
|
|
SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
|
|
|
|
|
|
|
|
|
|
if (pRxData) {
|
|
|
|
|
int idx = 0;
|
|
|
|
|
// Read data out
|
|
|
|
|
do {
|
|
|
|
|
*pRxData++ = READ_PERI_REG(SPI_W0_REG(spi_num) + (idx << 2));
|
|
|
|
|
} while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0)));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static uint32_t backup_usr[3];
|
|
|
|
|
static uint32_t backup_usr1[3];
|
|
|
|
|
static uint32_t backup_usr2[3];
|
|
|
|
|
|
|
|
|
|
//setup spi command/addr/data/dummy in user mode
|
|
|
|
|
static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t* pInData)
|
|
|
|
|
{
|
|
|
|
|
while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
|
|
|
|
|
backup_usr[spi_num]=READ_PERI_REG(SPI_USER_REG(spi_num));
|
|
|
|
|
backup_usr1[spi_num]=READ_PERI_REG(SPI_USER1_REG(spi_num));
|
|
|
|
|
backup_usr2[spi_num]=READ_PERI_REG(SPI_USER2_REG(spi_num));
|
|
|
|
|
// Set command by user.
|
|
|
|
|
if (pInData->cmdBitLen != 0) {
|
|
|
|
|
// Max command length 16 bits.
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, pInData->cmdBitLen - 1,
|
|
|
|
|
SPI_USR_COMMAND_BITLEN_S);
|
|
|
|
|
// Enable command
|
|
|
|
|
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
|
|
|
|
|
// Load command,bit15-0 is cmd value.
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_VALUE, pInData->cmd, SPI_USR_COMMAND_VALUE_S);
|
|
|
|
|
} else {
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S);
|
|
|
|
|
}
|
|
|
|
|
// Set Address by user.
|
|
|
|
|
if (pInData->addrBitLen != 0) {
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, (pInData->addrBitLen - 1), SPI_USR_ADDR_BITLEN_S);
|
|
|
|
|
// Enable address
|
|
|
|
|
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
|
|
|
|
|
// Set address
|
|
|
|
|
WRITE_PERI_REG(SPI_ADDR_REG(spi_num), *pInData->addr);
|
|
|
|
|
} else {
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S);
|
|
|
|
|
}
|
|
|
|
|
// Set data by user.
|
|
|
|
|
uint32_t* p_tx_val = pInData->txData;
|
|
|
|
|
if (pInData->txDataBitLen != 0) {
|
|
|
|
|
// Enable MOSI
|
|
|
|
|
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
|
|
|
|
|
// Load send buffer
|
|
|
|
|
int len = (pInData->txDataBitLen + 31) / 32;
|
|
|
|
|
if (p_tx_val != NULL) {
|
|
|
|
|
memcpy((void*)SPI_W0_REG(spi_num), p_tx_val, len * 4);
|
|
|
|
|
}
|
|
|
|
|
// Set data send buffer length.Max data length 64 bytes.
|
|
|
|
|
SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1),
|
|
|
|
|
SPI_USR_MOSI_DBITLEN_S);
|
|
|
|
|
} else {
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, 0, SPI_USR_MOSI_DBITLEN_S);
|
|
|
|
|
}
|
|
|
|
|
// Set rx data by user.
|
|
|
|
|
if (pInData->rxDataBitLen != 0) {
|
|
|
|
|
// Enable MOSI
|
|
|
|
|
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
|
|
|
|
|
// Set data send buffer length.Max data length 64 bytes.
|
|
|
|
|
SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen - 1),
|
|
|
|
|
SPI_USR_MISO_DBITLEN_S);
|
|
|
|
|
} else {
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S);
|
|
|
|
|
}
|
|
|
|
|
if (pInData->dummyBitLen != 0) {
|
|
|
|
|
SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, pInData->dummyBitLen - 1,
|
|
|
|
|
SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
|
|
|
} else {
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, 0, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
|
|
|
}
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2018-07-03 23:43:30 -04:00
|
|
|
static void psram_cmd_end(int spi_num) {
|
2017-07-20 04:26:35 -04:00
|
|
|
while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
|
|
|
|
|
WRITE_PERI_REG(SPI_USER_REG(spi_num), backup_usr[spi_num]);
|
|
|
|
|
WRITE_PERI_REG(SPI_USER1_REG(spi_num), backup_usr1[spi_num]);
|
|
|
|
|
WRITE_PERI_REG(SPI_USER2_REG(spi_num), backup_usr2[spi_num]);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//exit QPI mode(set back to SPI mode)
|
|
|
|
|
static void psram_disable_qio_mode(psram_spi_num_t spi_num)
|
|
|
|
|
{
|
|
|
|
|
psram_cmd_t ps_cmd;
|
|
|
|
|
uint32_t cmd_exit_qpi;
|
2018-07-03 23:43:30 -04:00
|
|
|
cmd_exit_qpi = PSRAM_EXIT_QMODE;
|
|
|
|
|
ps_cmd.txDataBitLen = 8;
|
|
|
|
|
if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
|
|
|
|
|
switch (s_psram_mode) {
|
|
|
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
|
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
|
|
|
default:
|
|
|
|
|
cmd_exit_qpi = PSRAM_EXIT_QMODE << 8;
|
|
|
|
|
ps_cmd.txDataBitLen = 16;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2017-07-20 04:26:35 -04:00
|
|
|
}
|
|
|
|
|
ps_cmd.txData = &cmd_exit_qpi;
|
|
|
|
|
ps_cmd.cmd = 0;
|
|
|
|
|
ps_cmd.cmdBitLen = 0;
|
|
|
|
|
ps_cmd.addr = 0;
|
|
|
|
|
ps_cmd.addrBitLen = 0;
|
|
|
|
|
ps_cmd.rxData = NULL;
|
|
|
|
|
ps_cmd.rxDataBitLen = 0;
|
|
|
|
|
ps_cmd.dummyBitLen = 0;
|
|
|
|
|
psram_cmd_config(spi_num, &ps_cmd);
|
|
|
|
|
psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI);
|
|
|
|
|
psram_cmd_end(spi_num);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//read psram id
|
|
|
|
|
static void psram_read_id(uint32_t* dev_id)
|
|
|
|
|
{
|
|
|
|
|
psram_spi_num_t spi_num = PSRAM_SPI_1;
|
|
|
|
|
psram_disable_qio_mode(spi_num);
|
2018-07-03 23:43:30 -04:00
|
|
|
uint32_t dummy_bits = 0 + extra_dummy;
|
2017-07-20 04:26:35 -04:00
|
|
|
psram_cmd_t ps_cmd;
|
2018-07-03 23:43:30 -04:00
|
|
|
|
|
|
|
|
uint32_t addr = 0;
|
|
|
|
|
ps_cmd.addrBitLen = 3 * 8;
|
|
|
|
|
ps_cmd.cmd = PSRAM_DEVICE_ID;
|
|
|
|
|
ps_cmd.cmdBitLen = 8;
|
|
|
|
|
if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
|
|
|
|
|
switch (s_psram_mode) {
|
|
|
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
|
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
|
|
|
default:
|
|
|
|
|
ps_cmd.cmdBitLen = 2; //this two bits is used to delay 2 clock cycle
|
|
|
|
|
ps_cmd.cmd = 0;
|
|
|
|
|
addr = (PSRAM_DEVICE_ID << 24) | 0;
|
|
|
|
|
ps_cmd.addrBitLen = 4 * 8;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2017-07-20 04:26:35 -04:00
|
|
|
}
|
|
|
|
|
ps_cmd.addr = &addr;
|
|
|
|
|
ps_cmd.txDataBitLen = 0;
|
|
|
|
|
ps_cmd.txData = NULL;
|
|
|
|
|
ps_cmd.rxDataBitLen = 4 * 8;
|
|
|
|
|
ps_cmd.rxData = dev_id;
|
|
|
|
|
ps_cmd.dummyBitLen = dummy_bits;
|
2018-07-03 23:43:30 -04:00
|
|
|
|
2017-07-20 04:26:35 -04:00
|
|
|
psram_cmd_config(spi_num, &ps_cmd);
|
|
|
|
|
psram_clear_spi_fifo(spi_num);
|
|
|
|
|
psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
|
|
|
|
|
psram_cmd_end(spi_num);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//enter QPI mode
|
|
|
|
|
static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
|
|
|
|
|
{
|
|
|
|
|
psram_cmd_t ps_cmd;
|
|
|
|
|
uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0;
|
2018-07-03 23:43:30 -04:00
|
|
|
|
|
|
|
|
ps_cmd.cmdBitLen = 0;
|
|
|
|
|
if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
|
|
|
|
|
switch (s_psram_mode) {
|
|
|
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
|
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
|
|
|
default:
|
|
|
|
|
ps_cmd.cmdBitLen = 2;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2017-07-20 04:26:35 -04:00
|
|
|
}
|
|
|
|
|
ps_cmd.cmd = 0;
|
|
|
|
|
ps_cmd.addr = &addr;
|
|
|
|
|
ps_cmd.addrBitLen = 8;
|
|
|
|
|
ps_cmd.txData = NULL;
|
|
|
|
|
ps_cmd.txDataBitLen = 0;
|
|
|
|
|
ps_cmd.rxData = NULL;
|
|
|
|
|
ps_cmd.rxDataBitLen = 0;
|
|
|
|
|
ps_cmd.dummyBitLen = 0;
|
|
|
|
|
psram_cmd_config(spi_num, &ps_cmd);
|
|
|
|
|
psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
|
|
|
|
|
psram_cmd_end(spi_num);
|
|
|
|
|
return ESP_OK;
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-28 09:31:14 -04:00
|
|
|
void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode)
|
|
|
|
|
{
|
|
|
|
|
if (clk_mode == PSRAM_CLK_MODE_NORM) {
|
|
|
|
|
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
|
|
|
|
|
// Set cs time.
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, 1, SPI_HOLD_TIME_S);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, SPI_SETUP_TIME_S);
|
|
|
|
|
} else {
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_HOLD_M | SPI_CS_SETUP_M);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-07-20 04:26:35 -04:00
|
|
|
//spi param init for psram
|
|
|
|
|
void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
|
|
|
|
|
{
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_TRANS_DONE << 5);
|
|
|
|
|
// SPI_CPOL & SPI_CPHA
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_PIN_REG(spi_num), SPI_CK_IDLE_EDGE);
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CK_OUT_EDGE);
|
|
|
|
|
// SPI bit order
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_WR_BIT_ORDER);
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_RD_BIT_ORDER);
|
|
|
|
|
// SPI bit order
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_DOUTDIN);
|
|
|
|
|
// May be not must to do.
|
|
|
|
|
WRITE_PERI_REG(SPI_USER1_REG(spi_num), 0);
|
|
|
|
|
// SPI mode type
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_SLAVE_MODE);
|
|
|
|
|
memset((void*)SPI_W0_REG(spi_num), 0, 16 * 4);
|
2019-03-28 09:31:14 -04:00
|
|
|
psram_set_cs_timing(spi_num, s_clk_mode);
|
2017-07-20 04:26:35 -04:00
|
|
|
}
|
|
|
|
|
|
2019-05-07 04:36:37 -04:00
|
|
|
//psram gpio init , different working frequency we have different solutions
|
|
|
|
|
static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, psram_cache_mode_t mode)
|
2017-07-20 04:26:35 -04:00
|
|
|
{
|
2018-04-20 04:59:25 -04:00
|
|
|
int spi_cache_dummy = 0;
|
|
|
|
|
uint32_t rd_mode_reg = READ_PERI_REG(SPI_CTRL_REG(0));
|
2019-05-20 03:26:52 -04:00
|
|
|
if (rd_mode_reg & SPI_FREAD_QIO_M) {
|
2018-04-20 04:59:25 -04:00
|
|
|
spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN;
|
2019-05-20 03:26:52 -04:00
|
|
|
} else if (rd_mode_reg & SPI_FREAD_DIO_M) {
|
|
|
|
|
spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
|
2019-08-14 08:57:30 -04:00
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S);
|
2019-05-20 03:26:52 -04:00
|
|
|
} else if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) {
|
2018-04-20 04:59:25 -04:00
|
|
|
spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
|
|
|
|
|
} else {
|
|
|
|
|
spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
|
|
|
|
|
}
|
2017-07-20 04:26:35 -04:00
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
|
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
|
2018-04-20 04:59:25 -04:00
|
|
|
g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
|
|
|
|
|
g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
|
|
|
esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
|
|
|
|
|
esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
|
2017-11-03 03:10:47 -04:00
|
|
|
//set drive ability for clock
|
2019-05-07 04:36:37 -04:00
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 2, FUN_DRV_S);
|
2017-07-20 04:26:35 -04:00
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
|
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
|
2018-04-20 04:59:25 -04:00
|
|
|
g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
|
|
|
|
|
g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_80M;
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
|
|
|
esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT);
|
|
|
|
|
esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_FLASH_PORT);
|
2017-11-03 03:10:47 -04:00
|
|
|
//set drive ability for clock
|
2019-05-07 04:36:37 -04:00
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 3, FUN_DRV_S);
|
2017-07-20 04:26:35 -04:00
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
|
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
|
2018-04-20 04:59:25 -04:00
|
|
|
g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
|
|
|
g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
|
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
|
|
|
esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_CACHE_PORT);
|
|
|
|
|
esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT);
|
2017-11-03 03:10:47 -04:00
|
|
|
//set drive ability for clock
|
2019-05-07 04:36:37 -04:00
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV, 2, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV, 2, FUN_DRV_S);
|
2017-07-20 04:26:35 -04:00
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
2019-05-07 04:36:37 -04:00
|
|
|
SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_USR_DUMMY); // dummy enable
|
2017-07-20 04:26:35 -04:00
|
|
|
|
2019-05-07 04:36:37 -04:00
|
|
|
// In bootloader, all the signals are already configured,
|
|
|
|
|
// We keep the following code in case the bootloader is some older version.
|
|
|
|
|
gpio_matrix_out(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_out(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_out(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_in(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0);
|
|
|
|
|
gpio_matrix_out(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_in(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0);
|
|
|
|
|
gpio_matrix_out(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_in(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0);
|
|
|
|
|
gpio_matrix_out(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0);
|
|
|
|
|
|
2017-07-20 04:26:35 -04:00
|
|
|
//select pin function gpio
|
2019-05-07 04:36:37 -04:00
|
|
|
if ((psram_io->flash_clk_io == FLASH_CLK_IO) && (psram_io->flash_clk_io != psram_io->psram_clk_io)) {
|
|
|
|
|
//flash clock signal should come from IO MUX.
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUNC_SD_CLK_SPICLK);
|
|
|
|
|
} else {
|
|
|
|
|
//flash clock signal should come from GPIO matrix.
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], PIN_FUNC_GPIO);
|
|
|
|
|
}
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], PIN_FUNC_GPIO);
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], PIN_FUNC_GPIO);
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], PIN_FUNC_GPIO);
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], PIN_FUNC_GPIO);
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], PIN_FUNC_GPIO);
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], PIN_FUNC_GPIO);
|
|
|
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], PIN_FUNC_GPIO);
|
2019-03-28 09:31:14 -04:00
|
|
|
|
|
|
|
|
uint32_t flash_id = g_rom_flashchip.device_id;
|
|
|
|
|
if (flash_id == FLASH_ID_GD25LQ32C) {
|
|
|
|
|
// Set drive ability for 1.8v flash in 80Mhz.
|
2019-05-07 04:36:37 -04:00
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], FUN_DRV_V, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV_V, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], FUN_DRV_V, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV_V, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], FUN_DRV_V, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], FUN_DRV_V, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], FUN_DRV_V, 3, FUN_DRV_S);
|
|
|
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], FUN_DRV_V, 3, FUN_DRV_S);
|
2019-03-28 09:31:14 -04:00
|
|
|
}
|
2017-07-20 04:26:35 -04:00
|
|
|
}
|
|
|
|
|
|
2018-07-03 23:43:30 -04:00
|
|
|
psram_size_t psram_get_size()
|
|
|
|
|
{
|
2018-11-20 07:39:47 -05:00
|
|
|
if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || PSRAM_IS_64MBIT_TRIAL(s_psram_id)) {
|
2018-07-03 23:43:30 -04:00
|
|
|
return PSRAM_SIZE_64MBITS;
|
2018-11-20 07:39:47 -05:00
|
|
|
} else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) {
|
|
|
|
|
return PSRAM_SIZE_32MBITS;
|
|
|
|
|
} else if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) {
|
|
|
|
|
return PSRAM_SIZE_16MBITS;
|
2018-07-03 23:43:30 -04:00
|
|
|
} else {
|
|
|
|
|
return PSRAM_SIZE_MAX;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-07 04:36:37 -04:00
|
|
|
/*
|
|
|
|
|
* Psram mode init will overwrite original flash speed mode, so that it is possible to change psram and flash speed after OTA.
|
|
|
|
|
* Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
|
|
|
|
|
*/
|
2017-07-20 04:26:35 -04:00
|
|
|
esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
|
|
|
|
|
{
|
2019-06-13 04:24:45 -04:00
|
|
|
psram_io_t psram_io={0};
|
2017-11-03 03:10:47 -04:00
|
|
|
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
|
|
|
|
|
uint32_t pkg_ver = chip_ver & 0x7;
|
|
|
|
|
if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
|
2019-05-07 04:36:37 -04:00
|
|
|
ESP_EARLY_LOGI(TAG, "This chip is ESP32-D2WD");
|
|
|
|
|
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
|
|
|
|
|
if (cfg.tieh != RTC_VDDSDIO_TIEH_1_8V) {
|
|
|
|
|
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 1.8V");
|
|
|
|
|
return ESP_FAIL;
|
|
|
|
|
}
|
|
|
|
|
psram_io.psram_clk_io = D2WD_PSRAM_CLK_IO;
|
|
|
|
|
psram_io.psram_cs_io = D2WD_PSRAM_CS_IO;
|
2018-12-25 08:15:15 -05:00
|
|
|
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
|
|
|
|
|
ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO");
|
|
|
|
|
rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
|
|
|
|
|
if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
|
|
|
|
|
ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
|
|
|
|
|
return ESP_FAIL;
|
|
|
|
|
}
|
|
|
|
|
s_clk_mode = PSRAM_CLK_MODE_NORM;
|
2019-05-07 04:36:37 -04:00
|
|
|
psram_io.psram_clk_io = PICO_PSRAM_CLK_IO;
|
|
|
|
|
psram_io.psram_cs_io = PICO_PSRAM_CS_IO;
|
|
|
|
|
} else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)){
|
|
|
|
|
ESP_EARLY_LOGI(TAG, "This chip is ESP32-D0WD");
|
|
|
|
|
psram_io.psram_clk_io = D0WD_PSRAM_CLK_IO;
|
|
|
|
|
psram_io.psram_cs_io = D0WD_PSRAM_CS_IO;
|
2019-06-13 04:24:45 -04:00
|
|
|
} else {
|
|
|
|
|
ESP_EARLY_LOGE(TAG, "Not a valid or known package id: %d", pkg_ver);
|
|
|
|
|
abort();
|
2019-05-07 04:36:37 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const uint32_t spiconfig = ets_efuse_get_spiconfig();
|
|
|
|
|
if (spiconfig == EFUSE_SPICONFIG_SPI_DEFAULTS) {
|
2018-12-25 08:15:15 -05:00
|
|
|
psram_io.flash_clk_io = FLASH_CLK_IO;
|
|
|
|
|
psram_io.flash_cs_io = FLASH_CS_IO;
|
|
|
|
|
psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO;
|
|
|
|
|
psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO;
|
|
|
|
|
psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO;
|
|
|
|
|
psram_io.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO;
|
2019-05-07 04:36:37 -04:00
|
|
|
} else if (spiconfig == EFUSE_SPICONFIG_HSPI_DEFAULTS) {
|
|
|
|
|
psram_io.flash_clk_io = FLASH_HSPI_CLK_IO;
|
|
|
|
|
psram_io.flash_cs_io = FLASH_HSPI_CS_IO;
|
|
|
|
|
psram_io.psram_spiq_sd0_io = PSRAM_HSPI_SPIQ_SD0_IO;
|
|
|
|
|
psram_io.psram_spid_sd1_io = PSRAM_HSPI_SPID_SD1_IO;
|
|
|
|
|
psram_io.psram_spiwp_sd3_io = PSRAM_HSPI_SPIWP_SD3_IO;
|
|
|
|
|
psram_io.psram_spihd_sd2_io = PSRAM_HSPI_SPIHD_SD2_IO;
|
|
|
|
|
} else {
|
|
|
|
|
psram_io.flash_clk_io = EFUSE_SPICONFIG_RET_SPICLK(spiconfig);
|
|
|
|
|
psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig);
|
|
|
|
|
psram_io.psram_spiq_sd0_io = EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
|
|
|
|
|
psram_io.psram_spid_sd1_io = EFUSE_SPICONFIG_RET_SPID(spiconfig);
|
|
|
|
|
psram_io.psram_spihd_sd2_io = EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
|
|
|
|
|
|
|
|
|
|
// If flash mode is set to QIO or QOUT, the WP pin is equal the value configured in bootloader.
|
|
|
|
|
// If flash mode is set to DIO or DOUT, the WP pin should config it via menuconfig.
|
|
|
|
|
#if CONFIG_FLASHMODE_QIO || CONFIG_FLASHMODE_QOUT
|
|
|
|
|
psram_io.psram_spiwp_sd3_io = CONFIG_BOOTLOADER_SPI_WP_PIN;
|
|
|
|
|
#else
|
|
|
|
|
psram_io.psram_spiwp_sd3_io = CONFIG_SPIRAM_SPIWP_SD3_PIN;
|
|
|
|
|
#endif
|
2017-11-03 03:10:47 -04:00
|
|
|
}
|
|
|
|
|
|
2017-07-20 04:26:35 -04:00
|
|
|
assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
|
|
|
|
|
s_psram_mode = mode;
|
|
|
|
|
|
|
|
|
|
WRITE_PERI_REG(SPI_EXT3_REG(0), 0x1);
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M);
|
|
|
|
|
|
2018-12-25 08:15:15 -05:00
|
|
|
psram_spi_init(PSRAM_SPI_1, mode);
|
2019-03-28 09:31:14 -04:00
|
|
|
|
2017-07-20 04:26:35 -04:00
|
|
|
switch (mode) {
|
|
|
|
|
case PSRAM_CACHE_F80M_S80M:
|
2018-12-25 08:15:15 -05:00
|
|
|
gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
|
2017-07-20 04:26:35 -04:00
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
|
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
|
|
|
default:
|
2018-12-25 08:15:15 -05:00
|
|
|
if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
|
|
|
|
|
/* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral.
|
|
|
|
|
We do this by routing it signal to signal 224/225, which are used as a loopback; the extra run through
|
|
|
|
|
the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
|
|
|
|
|
silicon) as a temporary pad for this. So the signal path is:
|
|
|
|
|
SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK)
|
|
|
|
|
*/
|
2019-03-28 09:31:14 -04:00
|
|
|
gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0);
|
|
|
|
|
gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0);
|
2018-12-25 08:15:15 -05:00
|
|
|
gpio_matrix_out(psram_io.psram_clk_io, SIG_IN_FUNC225_IDX, 0, 0);
|
|
|
|
|
} else {
|
|
|
|
|
gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
|
|
|
|
|
}
|
2017-07-20 04:26:35 -04:00
|
|
|
break;
|
|
|
|
|
}
|
2019-05-07 04:36:37 -04:00
|
|
|
|
|
|
|
|
// Rise VDDSIO for 1.8V psram.
|
|
|
|
|
bootloader_common_vddsdio_configure();
|
2019-03-28 09:31:14 -04:00
|
|
|
// GPIO related settings
|
2019-05-07 04:36:37 -04:00
|
|
|
psram_gpio_config(&psram_io, mode);
|
2018-07-03 23:43:30 -04:00
|
|
|
psram_read_id(&s_psram_id);
|
|
|
|
|
if (!PSRAM_IS_VALID(s_psram_id)) {
|
|
|
|
|
return ESP_FAIL;
|
|
|
|
|
}
|
2019-05-07 04:36:37 -04:00
|
|
|
|
2018-11-20 07:39:47 -05:00
|
|
|
if (PSRAM_IS_32MBIT_VER0(s_psram_id)) {
|
2018-07-03 23:43:30 -04:00
|
|
|
s_clk_mode = PSRAM_CLK_MODE_DCLK;
|
|
|
|
|
if (mode == PSRAM_CACHE_F80M_S80M) {
|
2018-09-27 05:00:48 -04:00
|
|
|
/* note: If the third mode(80Mhz+80Mhz) is enabled for 32MBit 1V8 psram, VSPI port will be
|
|
|
|
|
occupied by the system.
|
2018-07-03 23:43:30 -04:00
|
|
|
Application code should never touch VSPI hardware in this case. We try to stop applications
|
2018-09-27 05:00:48 -04:00
|
|
|
from doing this using the drivers by claiming the port for ourselves */
|
2018-07-03 23:43:30 -04:00
|
|
|
periph_module_enable(PERIPH_VSPI_MODULE);
|
|
|
|
|
bool r=spicommon_periph_claim(VSPI_HOST);
|
|
|
|
|
if (!r) {
|
|
|
|
|
return ESP_ERR_INVALID_STATE;
|
|
|
|
|
}
|
2018-12-25 08:15:15 -05:00
|
|
|
gpio_matrix_out(psram_io.psram_clk_io, PSRAM_CLK_SIGNAL, 0, 0);
|
2018-07-03 23:43:30 -04:00
|
|
|
//use spi3 clock,but use spi1 data/cs wires
|
|
|
|
|
//We get a solid 80MHz clock from SPI3 by setting it up, starting a transaction, waiting until it
|
|
|
|
|
//is in progress, then cutting the clock (but not the reset!) to that peripheral.
|
2019-03-28 09:31:14 -04:00
|
|
|
WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_NUM), 32 << 24);
|
|
|
|
|
SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_NUM), SPI_FLASH_READ_M);
|
2018-07-03 23:43:30 -04:00
|
|
|
uint32_t spi_status;
|
|
|
|
|
while (1) {
|
2019-03-28 09:31:14 -04:00
|
|
|
spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_NUM));
|
2018-07-03 23:43:30 -04:00
|
|
|
if (spi_status != 0 && spi_status != 1) {
|
2019-03-28 09:31:14 -04:00
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, PSRAM_SPICLKEN);
|
2018-07-03 23:43:30 -04:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
2018-11-20 07:39:47 -05:00
|
|
|
} else {
|
|
|
|
|
// For other psram, we don't need any extra clock cycles after cs get back to high level
|
|
|
|
|
s_clk_mode = PSRAM_CLK_MODE_NORM;
|
|
|
|
|
gpio_matrix_out(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0);
|
|
|
|
|
gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0);
|
2018-12-25 08:15:15 -05:00
|
|
|
gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0);
|
2017-07-20 04:26:35 -04:00
|
|
|
}
|
2018-11-20 07:39:47 -05:00
|
|
|
|
2019-03-28 09:31:14 -04:00
|
|
|
// Update cs timing according to psram driving method.
|
|
|
|
|
psram_set_cs_timing(PSRAM_SPI_1, s_clk_mode);
|
|
|
|
|
psram_set_cs_timing(_SPI_CACHE_PORT, s_clk_mode);
|
2017-07-20 04:26:35 -04:00
|
|
|
psram_enable_qio_mode(PSRAM_SPI_1);
|
|
|
|
|
psram_cache_init(mode, vaddrmode);
|
|
|
|
|
return ESP_OK;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
//register initialization for sram cache params and r/w commands
|
|
|
|
|
static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
|
|
|
|
|
{
|
|
|
|
|
switch (psram_cache_mode) {
|
|
|
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk,80+40;
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4
|
|
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F80M_S40M:
|
2019-04-08 05:36:12 -04:00
|
|
|
CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0, SPI_CLKDIV_PRE_S);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S);
|
2017-07-20 04:26:35 -04:00
|
|
|
SET_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
|
|
|
|
|
break;
|
|
|
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
|
|
|
default:
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div
|
|
|
|
|
break;
|
|
|
|
|
}
|
2019-05-07 04:36:37 -04:00
|
|
|
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M); //disable dio mode for cache command
|
|
|
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_QIO_M); //enable qio mode for cache command
|
|
|
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable cache read command
|
|
|
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_WCMD_M); //enable cache write command
|
2017-07-20 04:26:35 -04:00
|
|
|
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23, SPI_SRAM_ADDR_BITLEN_S); //write address for cache command.
|
2019-05-07 04:36:37 -04:00
|
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
2017-07-20 04:26:35 -04:00
|
|
|
|
2019-05-07 04:36:37 -04:00
|
|
|
//config sram cache r/w command
|
|
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
|
|
|
|
|
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD,
|
|
|
|
|
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB
|
2018-07-03 23:43:30 -04:00
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
|
|
|
|
|
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
|
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
|
|
|
|
|
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
|
2019-05-07 04:36:37 -04:00
|
|
|
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy; 80m--+2dummy
|
2017-07-20 04:26:35 -04:00
|
|
|
|
|
|
|
|
switch (psram_cache_mode) {
|
|
|
|
|
case PSRAM_CACHE_F80M_S80M: //in this mode , no delay is needed
|
|
|
|
|
break;
|
2019-05-07 04:36:37 -04:00
|
|
|
case PSRAM_CACHE_F80M_S40M: //if sram is @40M, need 2 cycles of delay
|
2017-07-20 04:26:35 -04:00
|
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
|
|
|
default:
|
2018-07-03 23:43:30 -04:00
|
|
|
if (s_clk_mode == PSRAM_CLK_MODE_DCLK) {
|
|
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
|
|
|
|
|
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
|
|
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, ((PSRAM_FAST_READ_QUAD) << 8),
|
2019-05-07 04:36:37 -04:00
|
|
|
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0xEB, read command value,(0x00 for delay,0xeb for cmd)
|
2018-07-03 23:43:30 -04:00
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
|
|
|
|
|
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
|
|
|
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, ((PSRAM_QUAD_WRITE) << 8),
|
|
|
|
|
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
|
|
|
|
|
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy,
|
2019-05-07 04:36:37 -04:00
|
|
|
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy; 80m--+2dummy
|
2018-07-03 23:43:30 -04:00
|
|
|
}
|
2017-07-20 04:26:35 -04:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
|
|
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
|
|
|
|
|
if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
|
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
|
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
|
|
|
|
|
} else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
|
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
|
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
|
|
|
|
|
//cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
|
|
|
|
DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S);
|
|
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
|
|
|
|
|
//cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
|
|
|
|
DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S);
|
|
|
|
|
|
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif // CONFIG_SPIRAM_SUPPORT
|
