esp-idf/tools/test_apps/build_system/ldgen_test/main/linker.lf

[mapping:main]
archive: libmain.a
entries:
    * (noflash)
    src1 (default)
    src1:func1 (noflash);
        text->iram0_text KEEP() ALIGN(9) ALIGN(12, post) SURROUND(sym1)
    src1:func0 (noflash);
        text->iram0_text KEEP()
    if SOC_RTC_MEM_SUPPORTED = y:
        src1:func2 (rtc)
ldgen: add test app for placement sanity check 2021-01-27 23:33:12 -05:00			`[mapping:main]`
			`archive: libmain.a`
			`entries:`
			`* (noflash)`
			`src1 (default)`
ci: update ldgen_test test_app to test flags 2021-02-03 05:20:17 -05:00			`src1:func1 (noflash);`
tools: fix ldgen_test fragment file KEEP 2021-03-10 23:04:40 -05:00			`text->iram0_text KEEP() ALIGN(9) ALIGN(12, post) SURROUND(sym1)`
feat(esp_system): allow .bss to spill over into L2MEM above 0x4ff40000 This commit introduce SOC_MEM_NON_CONTIGUOUS_SRAM flag (that enebled for esp32p4). If SOC_MEM_NON_CONTIGUOUS_SRAM is enabled: - LDFLAGS+=--enable-non-contiguous-regions - ldgen.py replaces "arrays[]" from sections.ld.in with objects under SURROUND keyword. (e.g. from linker.lf: data -> dram0_data SURROUND(foo)) - "mapping[]" - refers to all other data If SOC_MEM_NON_CONTIGUOUS_SRAM, sections.ld.in file should contain at least one block of code like this (otherwise it does not make sense): .dram0.bss (NOLOAD) : { arrays[dram0_bss] mapping[dram0_bss] } > sram_low .dram1.bss (NOLOAD) : { /* do not place here arrays[dram0_bss] because it may be splited * between segments */ mapping[dram0_bss] } > sram_high 2024-02-12 00:51:25 -05:00			`src1:func0 (noflash);`
			`text->iram0_text KEEP()`
ci: add pd_vddsdio in lightsleep UT tests - Add pd_vddsdio in lightsleep UT tests to ensure proper functionality 2023-06-07 07:51:06 -04:00			`if SOC_RTC_MEM_SUPPORTED = y:`
			`src1:func2 (rtc)`