mirror of
https://github.com/espressif/esp-idf.git
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281 lines
10 KiB
C
281 lines
10 KiB
C
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/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include "sdkconfig.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "unity.h"
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#include "driver/parlio_tx.h"
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#include "driver/gpio.h"
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#include "soc/soc_caps.h"
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#include "esp_attr.h"
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#include "test_board.h"
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#if CONFIG_PARLIO_ISR_IRAM_SAFE
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#define TEST_PARLIO_CALLBACK_ATTR IRAM_ATTR
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#else
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#define TEST_PARLIO_CALLBACK_ATTR
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#endif
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TEST_CASE("parallel_tx_unit_install_uninstall", "[parlio_tx]")
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{
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printf("install tx units exhaustively\r\n");
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parlio_tx_unit_handle_t units[SOC_PARLIO_GROUPS * SOC_PARLIO_TX_UNITS_PER_GROUP];
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int k = 0;
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parlio_tx_unit_config_t config = {
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.clk_src = PARLIO_CLK_SRC_DEFAULT,
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.data_width = SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH,
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.clk_in_gpio_num = -1, // clock source from internal
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.clk_out_gpio_num = 0,
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.output_clk_freq_hz = 1 * 1000 * 1000,
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.trans_queue_depth = 4,
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.max_transfer_size = 64,
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.valid_gpio_num = -1,
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};
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for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
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for (int j = 0; j < SOC_PARLIO_TX_UNITS_PER_GROUP; j++) {
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TEST_ESP_OK(parlio_new_tx_unit(&config, &units[k++]));
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}
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}
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TEST_ESP_ERR(ESP_ERR_NOT_FOUND, parlio_new_tx_unit(&config, &units[0]));
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for (int i = 0; i < k; i++) {
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TEST_ESP_OK(parlio_del_tx_unit(units[i]));
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}
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printf("install tx unit with valid signal and external core clock\r\n");
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// clock from external
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config.clk_in_gpio_num = 2;
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// failed because of invalid clock source frequency
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TEST_ESP_ERR(ESP_ERR_INVALID_ARG, parlio_new_tx_unit(&config, &units[0]));
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config.input_clk_src_freq_hz = 1000000;
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config.valid_gpio_num = 0;
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// failed because of data line conflict with valid signal
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TEST_ESP_ERR(ESP_ERR_INVALID_ARG, parlio_new_tx_unit(&config, &units[0]));
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config.data_width = 4;
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TEST_ESP_OK(parlio_new_tx_unit(&config, &units[0]));
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TEST_ESP_OK(parlio_tx_unit_enable(units[0]));
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// delete unit before it's disabled is not allowed
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TEST_ESP_ERR(ESP_ERR_INVALID_STATE, parlio_del_tx_unit(units[0]));
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TEST_ESP_OK(parlio_tx_unit_disable(units[0]));
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TEST_ESP_OK(parlio_del_tx_unit(units[0]));
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}
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TEST_PARLIO_CALLBACK_ATTR
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static bool test_parlio_tx_done_callback(parlio_tx_unit_handle_t tx_unit, const parlio_tx_done_event_data_t *edata, void *user_ctx)
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{
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BaseType_t high_task_wakeup = pdFALSE;
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TaskHandle_t task = (TaskHandle_t)user_ctx;
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vTaskNotifyGiveFromISR(task, &high_task_wakeup);
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return high_task_wakeup == pdTRUE;
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}
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TEST_CASE("parallel_tx_unit_trans_done_event", "[parlio_tx]")
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{
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printf("install parlio tx unit\r\n");
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parlio_tx_unit_handle_t tx_unit = NULL;
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parlio_tx_unit_config_t config = {
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.clk_src = PARLIO_CLK_SRC_DEFAULT,
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.data_width = 8,
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.clk_in_gpio_num = -1, // use internal clock source
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.valid_gpio_num = -1, // don't generate valid signal
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.clk_out_gpio_num = TEST_CLK_GPIO,
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.data_gpio_nums = {
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TEST_DATA0_GPIO,
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TEST_DATA1_GPIO,
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TEST_DATA2_GPIO,
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TEST_DATA3_GPIO,
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TEST_DATA4_GPIO,
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TEST_DATA5_GPIO,
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TEST_DATA6_GPIO,
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TEST_DATA7_GPIO,
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},
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.output_clk_freq_hz = 1 * 1000 * 1000,
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.trans_queue_depth = 8,
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.max_transfer_size = 128,
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.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
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.sample_edge = PARLIO_SAMPLE_EDGE_POS,
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};
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TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
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TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
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printf("register trans_done event callback\r\n");
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parlio_tx_event_callbacks_t cbs = {
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.on_trans_done = test_parlio_tx_done_callback,
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};
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TEST_ESP_OK(parlio_tx_unit_register_event_callbacks(tx_unit, &cbs, xTaskGetCurrentTaskHandle()));
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printf("send packets and check event is fired\r\n");
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parlio_transmit_config_t transmit_config = {
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.idle_value = 0x00,
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};
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uint8_t payload[64] = {0};
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for (int i = 0; i < 64; i++) {
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payload[i] = i;
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}
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TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload, 64 * sizeof(uint8_t) * 8, &transmit_config));
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TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, portMAX_DELAY));
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TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload, 64 * sizeof(uint8_t) * 8, &transmit_config));
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TEST_ASSERT_NOT_EQUAL(0, ulTaskNotifyTake(pdTRUE, portMAX_DELAY));
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TEST_ESP_OK(parlio_tx_unit_disable(tx_unit));
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TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
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};
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TEST_CASE("parallel_tx_unit_enable_disable", "[parlio_tx]")
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{
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printf("install parlio tx unit\r\n");
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parlio_tx_unit_handle_t tx_unit = NULL;
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parlio_tx_unit_config_t config = {
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.clk_src = PARLIO_CLK_SRC_DEFAULT,
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.data_width = 8,
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.clk_in_gpio_num = -1, // use internal clock source
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.valid_gpio_num = -1, // don't generate valid signal
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.clk_out_gpio_num = TEST_CLK_GPIO,
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.data_gpio_nums = {
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TEST_DATA0_GPIO,
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TEST_DATA1_GPIO,
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TEST_DATA2_GPIO,
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TEST_DATA3_GPIO,
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TEST_DATA4_GPIO,
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TEST_DATA5_GPIO,
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TEST_DATA6_GPIO,
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TEST_DATA7_GPIO,
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},
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.output_clk_freq_hz = 1 * 1000 * 1000,
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.trans_queue_depth = 64,
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.max_transfer_size = 256,
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.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
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.sample_edge = PARLIO_SAMPLE_EDGE_POS,
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};
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TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
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TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
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printf("send packets for multiple times\r\n");
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parlio_transmit_config_t transmit_config = {
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.idle_value = 0x00,
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};
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uint8_t payload[128] = {0};
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for (int i = 0; i < 128; i++) {
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payload[i] = i;
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}
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for (int j = 0; j < 64; j++) {
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TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload, 128 * sizeof(uint8_t) * 8, &transmit_config));
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}
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printf("disable the transaction in the middle\r\n");
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while (parlio_tx_unit_disable(tx_unit) != ESP_OK) {
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esp_rom_delay_us(1000);
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}
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vTaskDelay(pdMS_TO_TICKS(100));
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printf("resume the transaction and pending packets should continue\r\n");
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TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
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TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1));
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TEST_ESP_OK(parlio_tx_unit_disable(tx_unit));
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TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
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}
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TEST_CASE("parallel_tx_unit_idle_value", "[parlio_tx]")
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{
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printf("install parlio tx unit\r\n");
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parlio_tx_unit_handle_t tx_unit = NULL;
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parlio_tx_unit_config_t config = {
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.clk_src = PARLIO_CLK_SRC_DEFAULT,
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.data_width = 8,
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.clk_in_gpio_num = -1, // use internal clock source
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.valid_gpio_num = -1, // don't generate valid signal
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.clk_out_gpio_num = TEST_CLK_GPIO,
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.data_gpio_nums = {
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TEST_DATA0_GPIO,
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TEST_DATA1_GPIO,
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TEST_DATA2_GPIO,
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TEST_DATA3_GPIO,
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TEST_DATA4_GPIO,
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TEST_DATA5_GPIO,
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TEST_DATA6_GPIO,
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TEST_DATA7_GPIO,
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},
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.output_clk_freq_hz = 1 * 1000 * 1000,
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.trans_queue_depth = 4,
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.max_transfer_size = 64,
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.bit_pack_order = PARLIO_BIT_PACK_ORDER_LSB,
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.sample_edge = PARLIO_SAMPLE_EDGE_POS,
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.flags.io_loop_back = 1, // enable loop back by GPIO matrix, so that we can read the level of the data line by gpio driver
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};
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TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
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TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
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printf("send packet with different idle_value\r\n");
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parlio_transmit_config_t transmit_config = {
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.idle_value = 0x00,
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};
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uint8_t payload[8] = {0};
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for (int i = 0; i < 8; i++) {
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payload[i] = i;
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}
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for (int j = 0; j < 16; j++) {
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transmit_config.idle_value = j;
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TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload, sizeof(payload) * 8, &transmit_config));
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TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, 100));
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TEST_ASSERT_EQUAL(j & 0x01, gpio_get_level(TEST_DATA0_GPIO));
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}
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TEST_ESP_OK(parlio_tx_unit_disable(tx_unit));
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TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
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}
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#if SOC_PARLIO_TX_CLK_SUPPORT_GATING
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TEST_CASE("parallel_tx_clock_gating", "[paralio_tx]")
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{
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printf("install parlio tx unit\r\n");
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parlio_tx_unit_handle_t tx_unit = NULL;
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parlio_tx_unit_config_t config = {
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.clk_src = PARLIO_CLK_SRC_DEFAULT,
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.data_width = 2,
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.clk_in_gpio_num = -1, // use internal clock source
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.valid_gpio_num = TEST_DATA7_GPIO, // generate the valid signal
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.clk_out_gpio_num = TEST_CLK_GPIO,
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.data_gpio_nums = {
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TEST_DATA0_GPIO,
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TEST_DATA1_GPIO,
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},
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.output_clk_freq_hz = 1 * 1000 * 1000,
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.trans_queue_depth = 4,
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.max_transfer_size = 64,
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.bit_pack_order = PARLIO_BIT_PACK_ORDER_MSB,
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.sample_edge = PARLIO_SAMPLE_EDGE_POS,
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.flags.clk_gate_en = true, // enable clock gating, controlled by the level of TEST_DATA7_GPIO
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.flags.io_loop_back = true, // for reading the level of the clock line in IDLE state
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};
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TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
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TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
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printf("send packets and see if the clock is gated when there's no transaction on line\r\n");
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parlio_transmit_config_t transmit_config = {
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.idle_value = 0x00,
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};
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uint8_t payload[8] = {0};
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for (int i = 0; i < 8; i++) {
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payload[i] = 0x1B; // 8'b00011011, in PARLIO_BIT_PACK_ORDER_MSB, you should see 2'b00, 2'b01, 2'b10, 2'b11 on the data line
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}
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TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload, 8 * sizeof(uint8_t) * 8, &transmit_config));
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TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1));
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// check if the level on the clock line is low
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TEST_ASSERT_EQUAL(0, gpio_get_level(TEST_CLK_GPIO));
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TEST_ESP_OK(parlio_tx_unit_transmit(tx_unit, payload, 8 * sizeof(uint8_t) * 8, &transmit_config));
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TEST_ESP_OK(parlio_tx_unit_wait_all_done(tx_unit, -1));
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TEST_ASSERT_EQUAL(0, gpio_get_level(TEST_CLK_GPIO));
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TEST_ASSERT_EQUAL(0, gpio_get_level(TEST_CLK_GPIO));
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TEST_ESP_OK(parlio_tx_unit_disable(tx_unit));
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TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
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}
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#endif // SOC_PARLIO_TX_CLK_SUPPORT_GATING
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