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esp-idf/components/freertos/FreeRTOS-Kernel/portable/riscv/portasm.S

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freertos: Add SPDX license identifiers and update xtensa port files This commit does the following: - Adds SPDX license identifiers to FreeRTOS sources. Remove those FreeRTOS sources from the copyright ignore list. - Update xtensa port files to match FreeRTOS v10.4.3. Added SPDX license identifiers to the port files. - Fixed some improperly licensed files - Removed portbenchmark.h from RISC-V port
2022-01-29 03:49:56 -05:00
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
.global uxInterruptNesting
.global uxSchedulerRunning
.global xIsrStackTop
.global pxCurrentTCB
.global vTaskSwitchContext
.global xPortSwitchFlag
.section .text
/**
* This function makes the RTOS aware about a ISR entering, it takes the
* current task stack saved, places into the TCB, loads the ISR stack
* the interrupted stack must be passed in a0. It needs to receive the
* ISR nesting code improvements
*/
.global rtos_int_enter
.type rtos_int_enter, @function
rtos_int_enter:
/* preserve the return address */
mv t1, ra
mv t2, a0
/* scheduler not enabled, jump directly to ISR handler */
esp32c3: format and clean up interrupt and os port code
2020-12-28 23:31:54 -05:00
lw t0, uxSchedulerRunning
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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beq t0,zero, rtos_enter_end
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
2020-11-04 16:34:47 -05:00
/* increments the ISR nesting count */
la t3, uxInterruptNesting
lw t4, 0x0(t3)
addi t5,t4,1
sw t5, 0x0(t3)
esp32c3: format and clean up interrupt and os port code
2020-12-28 23:31:54 -05:00
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
2020-11-04 16:34:47 -05:00
/* If reached here from another low-prio ISR, skip stack pushing to TCB */
bne t4,zero, rtos_enter_end
/* Save current TCB and load the ISR stack */
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
lw t0, pxCurrentTCB
sw t2, 0x0(t0)
lw sp, xIsrStackTop
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
2020-11-04 16:34:47 -05:00
rtos_enter_end:
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
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mv ra, t1
ret
/**
* Recovers the next task to run stack pointer and place it into
* a0, then the interrupt handler can restore the context of
* the next task
*/
.global rtos_int_exit
.type rtos_int_exit, @function
rtos_int_exit:
/* may skip RTOS aware interrupt since scheduler was not started */
esp32c3: format and clean up interrupt and os port code
2020-12-28 23:31:54 -05:00
lw t0, uxSchedulerRunning
beq t0,zero, rtos_exit_end
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
2020-11-04 16:34:47 -05:00
/* update nesting interrupts counter */
freertos: riscv port now uses interrupt allocator and crosscore interrupt
2020-11-13 14:03:50 -05:00
la t2, uxInterruptNesting
lw t3, 0x0(t2)
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
2020-11-04 16:34:47 -05:00
interrupt-allocator: reject vector allocation if its marked as not-implemented. and search to next available
2020-11-19 13:14:54 -05:00
/* Already zero, protect against underflow */
freertos: riscv port now uses interrupt allocator and crosscore interrupt
2020-11-13 14:03:50 -05:00
beq t3, zero, isr_skip_decrement
addi t3,t3, -1
sw t3, 0x0(t2)
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
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isr_skip_decrement:
freertos: riscv port now uses interrupt allocator and crosscore interrupt
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/* may still have interrupts pending, skip section below and exit */
esp32c3: format and clean up interrupt and os port code
2020-12-28 23:31:54 -05:00
bne t3,zero,rtos_exit_end
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
/* Schedule the next task if a yield is pending */
la t0, xPortSwitchFlag
lw t2, 0x0(t0)
beq t2, zero, no_switch
core: fix cases where riscv SP were not 16 byte aligned RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.
2021-02-18 22:26:21 -05:00
/* preserve return address and schedule next task
stack pointer for riscv should always be 16 byte aligned */
addi sp,sp,-16
freerots: fix rtos_int_exit writing outside ISR stack rtos_int_exit would store RA at an offset of 4 byte from the SP, where the offset should be 0. This caused rtos_int_exit to overwrite variables in bss.
2021-01-26 06:05:41 -05:00
sw ra, 0(sp)
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
call vTaskSwitchContext
freerots: fix rtos_int_exit writing outside ISR stack rtos_int_exit would store RA at an offset of 4 byte from the SP, where the offset should be 0. This caused rtos_int_exit to overwrite variables in bss.
2021-01-26 06:05:41 -05:00
lw ra, 0(sp)
core: fix cases where riscv SP were not 16 byte aligned RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.
2021-02-18 22:26:21 -05:00
addi sp, sp, 16
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
/* Clears the switch pending flag */
la t0, xPortSwitchFlag
mv t2, zero
sw t2, 0x0(t0)
no_switch:
/* Recover the stack of next task and prepare to exit : */
lw a0, pxCurrentTCB
lw a0, 0x0(a0)
freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. The riscv vectors.S in riscv component contains the trap vector, which is responsible to defer interrupts and examine if a task context switch is needed, this change cleans up this code by hiding all freertos details behind on two functions rtos_it_enter/exit and their implementations are placed in freertos riscv port files.
2020-11-04 16:34:47 -05:00
rtos_exit_end:
freertos: Add RISC-V port Changes come from internal branch commit a6723fc
2020-11-05 23:03:21 -05:00
ret
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