2019-12-25 04:32:12 -05:00
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# This example supports running on the SPI1 bus, which is shared with SPI flash accessed by the
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# cache. When doing transaction on SPI1 bus, data cannot be fetched from the flash, so all the data
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# used during this time should be put into the internal RAM.
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[mapping:eeprom]
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archive: libeeprom.a
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entries:
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2023-10-17 00:11:42 -04:00
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if EXAMPLE_USE_SPI1_PINS = y:
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* (noflash)
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2023-11-07 21:51:04 -05:00
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# Following code are not used during SPI1 bus or bus option
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spi_eeprom: eeprom_wait_done_by_intr (default)
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spi_eeprom: spi_eeprom_deinit (default)
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spi_eeprom: spi_eeprom_init (default)
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2019-12-25 04:32:12 -05:00
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[mapping:ext_newlib]
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archive: libnewlib.a
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entries:
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2023-10-17 00:11:42 -04:00
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if EXAMPLE_USE_SPI1_PINS = y:
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time:usleep (noflash)
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