esp-idf/components/esp_rom/esp32c2/Kconfig.soc_caps.in

#####################################################
# This file is auto-generated from SoC caps
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################

config ESP_ROM_HAS_CRC_LE
    bool
    default y

config ESP_ROM_HAS_CRC_BE
    bool
    default y

config ESP_ROM_UART_CLK_IS_XTAL
    bool
    default y

config ESP_ROM_HAS_RETARGETABLE_LOCKING
    bool
    default y

config ESP_ROM_GET_CLK_FREQ
    bool
    default y

config ESP_ROM_HAS_RVFPLIB
    bool
    default y

config ESP_ROM_HAS_HAL_WDT
    bool
    default y

config ESP_ROM_HAS_HAL_SYSTIMER
    bool
    default y

config ESP_ROM_HAS_HEAP_TLSF
    bool
    default y

config ESP_ROM_TLSF_CHECK_PATCH
    bool
    default y

config ESP_ROM_HAS_LAYOUT_TABLE
    bool
    default y

config ESP_ROM_HAS_SPI_FLASH
    bool
    default y

config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
    bool
    default y

config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
    bool
    default y

config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
    bool
    default y
build-system: include soc_caps defines into kconfig Adds gen_soc_caps_kconfig.py which parses the soc caps (soc_caps.h) into a format that can be included in kconfig. 2021-11-05 17:23:24 +08:00			`#####################################################`
			`# This file is auto-generated from SoC caps`
			`# using gen_soc_caps_kconfig.py, do not edit manually`
			`#####################################################`

			`config ESP_ROM_HAS_CRC_LE`
			`bool`
			`default y`

			`config ESP_ROM_HAS_CRC_BE`
			`bool`
			`default y`

			`config ESP_ROM_UART_CLK_IS_XTAL`
			`bool`
			`default y`

			`config ESP_ROM_HAS_RETARGETABLE_LOCKING`
			`bool`
			`default y`

			`config ESP_ROM_GET_CLK_FREQ`
			`bool`
			`default y`
esp32c2: Support riscv floating-point library selection 2022-05-08 17:57:40 +08:00
			`config ESP_ROM_HAS_RVFPLIB`
			`bool`
			`default y`
hal: use ROM implementation for systimer and wdt on esp32c2 2022-05-06 18:57:14 +08:00
			`config ESP_ROM_HAS_HAL_WDT`
			`bool`
			`default y`

			`config ESP_ROM_HAS_HAL_SYSTIMER`
			`bool`
			`default y`
heap: use ROM implementation for heap tlsf on esp32c2 2022-05-06 19:20:05 +08:00
			`config ESP_ROM_HAS_HEAP_TLSF`
			`bool`
			`default y`
esp-rom: create a patch of tlsf_check() for target(s) supporting ROM implementation of TLSF The tlsf implementation in the ROM does not provide a mechanism to register a callback to be called in by tlsf_check(). This commit is creating a patch of the tlsf implementation to provide a definition of the function allowing to register the callback called in tlsf_check() and add the call of this callback in tlsf_check(). This patch is only compiled for target(s) with ESP_ROM_HAS_HEAP_TLSF set and ESP_ROM_TLSF_CHECK_PATCH set. For all the other configurations the environment remains unchanged by those modifications. 2022-08-12 11:28:16 +02:00
			`config ESP_ROM_TLSF_CHECK_PATCH`
			`bool`
			`default y`
esp32c6: add esp_rom support (rom version: esp32c6-20220901) 2022-07-12 20:28:06 +08:00
			`config ESP_ROM_HAS_LAYOUT_TABLE`
			`bool`
			`default y`

			`config ESP_ROM_HAS_SPI_FLASH`
			`bool`
			`default y`
newlib: update newlib nano documentation for C6 C6 ROM has the the full IO formatting functions included. 2023-02-02 17:24:31 +08:00
			`config ESP_ROM_HAS_NEWLIB_NANO_FORMAT`
			`bool`
			`default y`
esp_rom: add macro ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE for S3/C3/C2/C6/H2/H4 2023-03-06 16:49:10 +08:00
			`config ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE`
			`bool`
			`default y`
system: fixed ram app cannot use mmu correctly issue 2023-03-09 14:45:45 +08:00
			`config ESP_ROM_RAM_APP_NEEDS_MMU_INIT`
			`bool`
			`default y`