2019-04-18 10:13:05 -04:00
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#include "hal/spi_slave_hal.h"
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#include "hal/spi_ll.h"
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2020-09-23 09:01:13 -04:00
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#include "soc/soc_caps.h"
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2019-04-18 10:13:05 -04:00
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bool spi_slave_hal_usr_is_done(spi_slave_hal_context_t* hal)
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{
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return spi_ll_usr_is_done(hal->hw);
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}
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void spi_slave_hal_user_start(const spi_slave_hal_context_t *hal)
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{
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spi_ll_clear_int_stat(hal->hw); //clear int bit
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2023-07-04 21:46:21 -04:00
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spi_ll_user_start(hal->hw);
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2019-04-18 10:13:05 -04:00
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}
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2023-12-12 23:51:58 -05:00
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void spi_slave_hal_hw_prepare_rx(spi_dev_t *hw)
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2023-09-01 05:51:54 -04:00
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{
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2023-12-12 23:51:58 -05:00
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spi_ll_dma_rx_fifo_reset(hw);
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spi_ll_infifo_full_clr(hw);
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spi_ll_dma_rx_enable(hw, 1);
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2023-09-01 05:51:54 -04:00
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}
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2023-12-12 23:51:58 -05:00
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void spi_slave_hal_hw_prepare_tx(spi_dev_t *hw)
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2019-04-18 10:13:05 -04:00
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{
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2023-12-12 23:51:58 -05:00
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spi_ll_dma_tx_fifo_reset(hw);
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spi_ll_outfifo_empty_clr(hw);
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spi_ll_dma_tx_enable(hw, 1);
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}
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2023-08-31 07:17:40 -04:00
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2023-12-12 23:51:58 -05:00
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void spi_slave_hal_hw_reset(spi_slave_hal_context_t *hal)
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{
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spi_ll_slave_reset(hal->hw);
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}
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2020-09-14 05:33:10 -04:00
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2023-12-12 23:51:58 -05:00
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void spi_slave_hal_hw_fifo_reset(spi_slave_hal_context_t *hal, bool tx_rst, bool rx_rst)
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{
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tx_rst ? spi_ll_cpu_tx_fifo_reset(hal->hw) : 0;
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rx_rst ? spi_ll_cpu_rx_fifo_reset(hal->hw) : 0;
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}
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2020-11-10 02:40:01 -05:00
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2023-12-12 23:51:58 -05:00
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void spi_slave_hal_push_tx_buffer(spi_slave_hal_context_t *hal)
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{
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if (hal->tx_buffer) {
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spi_ll_write_buffer(hal->hw, hal->tx_buffer, hal->bitlen);
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2019-04-18 10:13:05 -04:00
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}
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2023-12-12 23:51:58 -05:00
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}
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2020-11-10 02:40:01 -05:00
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2023-12-12 23:51:58 -05:00
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void spi_slave_hal_set_trans_bitlen(spi_slave_hal_context_t *hal)
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{
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2019-04-18 10:13:05 -04:00
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spi_ll_slave_set_rx_bitlen(hal->hw, hal->bitlen);
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spi_ll_slave_set_tx_bitlen(hal->hw, hal->bitlen);
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2023-12-12 23:51:58 -05:00
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}
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2020-09-14 05:33:10 -04:00
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2023-12-12 23:51:58 -05:00
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void spi_slave_hal_enable_data_line(spi_slave_hal_context_t *hal)
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{
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spi_ll_enable_mosi(hal->hw, (hal->rx_buffer != NULL));
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spi_ll_enable_miso(hal->hw, (hal->tx_buffer != NULL));
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2019-04-18 10:13:05 -04:00
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}
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void spi_slave_hal_store_result(spi_slave_hal_context_t *hal)
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{
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//when data of cur_trans->length are all sent, the slv_rdata_bit
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//will be the length sent-1 (i.e. cur_trans->length-1 ), otherwise
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//the length sent.
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hal->rcv_bitlen = spi_ll_slave_get_rcv_bitlen(hal->hw);
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if (hal->rcv_bitlen == hal->bitlen - 1) {
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hal->rcv_bitlen++;
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}
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if (!hal->use_dma && hal->rx_buffer) {
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//Copy result out
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spi_ll_read_buffer(hal->hw, hal->rx_buffer, hal->bitlen);
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}
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}
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uint32_t spi_slave_hal_get_rcv_bitlen(spi_slave_hal_context_t *hal)
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{
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return hal->rcv_bitlen;
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}
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2022-09-15 06:26:12 -04:00
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#if CONFIG_IDF_TARGET_ESP32
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//This workaround is only for esp32
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2019-04-18 10:13:05 -04:00
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bool spi_slave_hal_dma_need_reset(const spi_slave_hal_context_t *hal)
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{
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bool ret;
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ret = false;
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if (hal->use_dma && hal->rx_buffer) {
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int i;
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//In case CS goes high too soon, the transfer is aborted while the DMA channel still thinks it's going. This
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//leads to issues later on, so in that case we need to reset the channel. The state can be detected because
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//the DMA system doesn't give back the offending descriptor; the owner is still set to DMA.
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2023-09-01 05:51:54 -04:00
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for (i = 0; hal->dmadesc_rx[i].dw0.suc_eof == 0 && hal->dmadesc_rx[i].dw0.owner == 0; i++) {}
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if (hal->dmadesc_rx[i].dw0.owner) {
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2019-04-18 10:13:05 -04:00
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ret = true;
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}
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}
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return ret;
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2020-09-08 05:05:49 -04:00
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}
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2022-09-15 06:26:12 -04:00
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#endif //#if CONFIG_IDF_TARGET_ESP32
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