2018-06-20 07:59:11 -04:00
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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2018-08-22 06:16:32 -04:00
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* Adaptations to ESP-IDF Copyright (c) 2016-2018 Espressif Systems (Shanghai) PTE LTD
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2018-06-20 07:59:11 -04:00
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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2023-10-17 10:13:32 -04:00
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#include <inttypes.h>
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2018-06-20 07:59:11 -04:00
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#include "sdmmc_common.h"
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static const char* TAG = "sdmmc_common";
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esp_err_t sdmmc_init_ocr(sdmmc_card_t* card)
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{
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esp_err_t err;
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/* In SPI mode, READ_OCR (CMD58) command is used to figure out which voltage
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* ranges the card can support. This step is skipped since 1.8V isn't
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* supported on the ESP32.
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*/
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uint32_t host_ocr = get_host_ocr(card->host.io_voltage);
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2024-02-27 06:19:19 -05:00
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/* In SPI mode, the only non-zero bit of ACMD41 is HCS (bit 30)
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* In SD mode, bits 23:8 contain the supported voltage mask
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*/
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uint32_t acmd41_arg = 0;
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if (!host_is_spi(card)) {
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acmd41_arg = host_ocr;
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}
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2018-06-20 07:59:11 -04:00
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if ((card->ocr & SD_OCR_SDHC_CAP) != 0) {
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2024-02-27 06:19:19 -05:00
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acmd41_arg |= SD_OCR_SDHC_CAP;
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2018-06-20 07:59:11 -04:00
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}
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2024-02-27 06:19:19 -05:00
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2018-06-20 07:59:11 -04:00
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/* Send SEND_OP_COND (ACMD41) command to the card until it becomes ready. */
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2024-02-27 06:19:19 -05:00
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err = sdmmc_send_cmd_send_op_cond(card, acmd41_arg, &card->ocr);
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2018-06-20 07:59:11 -04:00
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/* If time-out, re-try send_op_cond as MMC */
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if (err == ESP_ERR_TIMEOUT && !host_is_spi(card)) {
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ESP_LOGD(TAG, "send_op_cond timeout, trying MMC");
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card->is_mmc = 1;
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2024-02-27 06:19:19 -05:00
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err = sdmmc_send_cmd_send_op_cond(card, acmd41_arg, &card->ocr);
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2018-06-20 07:59:11 -04:00
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}
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "%s: send_op_cond (1) returned 0x%x", __func__, err);
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return err;
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}
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if (host_is_spi(card)) {
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err = sdmmc_send_cmd_read_ocr(card, &card->ocr);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "%s: read_ocr returned 0x%x", __func__, err);
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return err;
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}
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}
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2023-10-17 10:13:32 -04:00
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ESP_LOGD(TAG, "host_ocr=0x%" PRIx32 " card_ocr=0x%" PRIx32, host_ocr, card->ocr);
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2018-06-20 07:59:11 -04:00
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/* Clear all voltage bits in host's OCR which the card doesn't support.
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* Don't touch CCS bit because in SPI mode cards don't report CCS in ACMD41
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* response.
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*/
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host_ocr &= (card->ocr | (~SD_OCR_VOL_MASK));
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2023-10-17 10:13:32 -04:00
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ESP_LOGD(TAG, "sdmmc_card_init: host_ocr=%08" PRIx32 ", card_ocr=%08" PRIx32, host_ocr, card->ocr);
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2018-06-20 07:59:11 -04:00
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return ESP_OK;
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}
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esp_err_t sdmmc_init_cid(sdmmc_card_t* card)
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{
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esp_err_t err;
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sdmmc_response_t raw_cid;
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if (!host_is_spi(card)) {
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2018-12-28 13:04:37 -05:00
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err = sdmmc_send_cmd_all_send_cid(card, &raw_cid);
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2018-06-20 07:59:11 -04:00
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if (err != ESP_OK) {
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2018-12-28 13:04:37 -05:00
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ESP_LOGE(TAG, "%s: all_send_cid returned 0x%x", __func__, err);
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2018-06-20 07:59:11 -04:00
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return err;
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}
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2018-12-28 13:04:37 -05:00
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if (!card->is_mmc) {
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err = sdmmc_decode_cid(raw_cid, &card->cid);
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2018-06-20 07:59:11 -04:00
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if (err != ESP_OK) {
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2018-12-28 13:04:37 -05:00
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ESP_LOGE(TAG, "%s: decoding CID failed (0x%x)", __func__, err);
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2018-06-20 07:59:11 -04:00
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return err;
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}
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} else {
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2018-12-28 13:04:37 -05:00
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/* For MMC, need to know CSD to decode CID. But CSD can only be read
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* in data transfer mode, and it is not possible to read CID in data
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* transfer mode. We temporiliy store the raw cid and do the
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* decoding after the RCA is set and the card is in data transfer
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* mode.
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*/
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memcpy(card->raw_cid, raw_cid, sizeof(sdmmc_response_t));
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2018-06-20 07:59:11 -04:00
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}
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} else {
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err = sdmmc_send_cmd_send_cid(card, &card->cid);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "%s: send_cid returned 0x%x", __func__, err);
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return err;
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}
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}
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return ESP_OK;
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}
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2018-12-28 13:04:37 -05:00
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esp_err_t sdmmc_init_rca(sdmmc_card_t* card)
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{
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esp_err_t err;
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err = sdmmc_send_cmd_set_relative_addr(card, &card->rca);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "%s: set_relative_addr returned 0x%x", __func__, err);
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return err;
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}
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return ESP_OK;
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}
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esp_err_t sdmmc_init_mmc_decode_cid(sdmmc_card_t* card)
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{
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esp_err_t err;
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sdmmc_response_t raw_cid;
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memcpy(raw_cid, card->raw_cid, sizeof(raw_cid));
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err = sdmmc_mmc_decode_cid(card->csd.mmc_ver, raw_cid, &card->cid);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "%s: decoding CID failed (0x%x)", __func__, err);
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return err;
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}
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return ESP_OK;
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}
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2018-06-20 07:59:11 -04:00
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esp_err_t sdmmc_init_csd(sdmmc_card_t* card)
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{
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2018-09-24 22:58:43 -04:00
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assert(card->is_mem == 1);
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2018-06-20 07:59:11 -04:00
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/* Get and decode the contents of CSD register. Determine card capacity. */
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esp_err_t err = sdmmc_send_cmd_send_csd(card, &card->csd);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "%s: send_csd returned 0x%x", __func__, err);
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return err;
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}
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const size_t max_sdsc_capacity = UINT32_MAX / card->csd.sector_size + 1;
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if (!(card->ocr & SD_OCR_SDHC_CAP) &&
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card->csd.capacity > max_sdsc_capacity) {
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ESP_LOGW(TAG, "%s: SDSC card reports capacity=%u. Limiting to %u.",
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__func__, card->csd.capacity, max_sdsc_capacity);
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card->csd.capacity = max_sdsc_capacity;
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}
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return ESP_OK;
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}
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esp_err_t sdmmc_init_select_card(sdmmc_card_t* card)
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{
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assert(!host_is_spi(card));
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esp_err_t err = sdmmc_send_cmd_select_card(card, card->rca);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "%s: select_card returned 0x%x", __func__, err);
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return err;
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}
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return ESP_OK;
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}
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esp_err_t sdmmc_init_card_hs_mode(sdmmc_card_t* card)
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{
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esp_err_t err = ESP_ERR_NOT_SUPPORTED;
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if (card->is_mem && !card->is_mmc) {
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err = sdmmc_enable_hs_mode_and_check(card);
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} else if (card->is_sdio) {
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err = sdmmc_io_enable_hs_mode(card);
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} else if (card->is_mmc){
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err = sdmmc_mmc_enable_hs_mode(card);
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}
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if (err == ESP_ERR_NOT_SUPPORTED) {
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ESP_LOGD(TAG, "%s: host supports HS mode, but card doesn't", __func__);
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card->max_freq_khz = SDMMC_FREQ_DEFAULT;
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} else if (err != ESP_OK) {
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return err;
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}
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return ESP_OK;
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}
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esp_err_t sdmmc_init_host_bus_width(sdmmc_card_t* card)
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{
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int bus_width = 1;
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if ((card->host.flags & SDMMC_HOST_FLAG_4BIT) &&
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(card->log_bus_width == 2)) {
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bus_width = 4;
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} else if ((card->host.flags & SDMMC_HOST_FLAG_8BIT) &&
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(card->log_bus_width == 3)) {
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bus_width = 8;
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}
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ESP_LOGD(TAG, "%s: using %d-bit bus", __func__, bus_width);
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if (bus_width > 1) {
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esp_err_t err = (*card->host.set_bus_width)(card->host.slot, bus_width);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "host.set_bus_width failed (0x%x)", err);
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return err;
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}
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}
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return ESP_OK;
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}
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esp_err_t sdmmc_init_host_frequency(sdmmc_card_t* card)
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{
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2023-03-23 18:27:29 -04:00
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esp_err_t err;
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2018-06-20 07:59:11 -04:00
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assert(card->max_freq_khz <= card->host.max_freq_khz);
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2022-07-12 18:00:46 -04:00
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if (card->max_freq_khz > SDMMC_FREQ_PROBING) {
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2023-03-23 18:27:29 -04:00
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err = (*card->host.set_card_clk)(card->host.slot, card->max_freq_khz);
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2022-07-12 18:00:46 -04:00
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "failed to switch bus frequency (0x%x)", err);
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return err;
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2018-06-20 07:59:11 -04:00
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}
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2023-03-23 18:27:29 -04:00
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}
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2018-06-20 07:59:11 -04:00
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2023-04-18 07:50:01 -04:00
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if (card->host.input_delay_phase != SDMMC_DELAY_PHASE_0) {
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if (card->host.set_input_delay) {
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err = (*card->host.set_input_delay)(card->host.slot, card->host.input_delay_phase);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "host.set_input_delay failed (0x%x)", err);
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return err;
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}
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} else {
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ESP_LOGE(TAG, "input phase delay feature isn't supported");
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return ESP_ERR_NOT_SUPPORTED;
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}
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}
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2023-03-23 18:27:29 -04:00
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err = (*card->host.get_real_freq)(card->host.slot, &(card->real_freq_khz));
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "failed to get real working frequency (0x%x)", err);
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return err;
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2018-06-20 07:59:11 -04:00
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}
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2018-08-22 06:16:32 -04:00
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if (card->is_ddr) {
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if (card->host.set_bus_ddr_mode == NULL) {
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ESP_LOGE(TAG, "host doesn't support DDR mode or voltage switching");
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return ESP_ERR_NOT_SUPPORTED;
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}
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2023-03-23 18:27:29 -04:00
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err = (*card->host.set_bus_ddr_mode)(card->host.slot, true);
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2018-08-22 06:16:32 -04:00
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "failed to switch bus to DDR mode (0x%x)", err);
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return err;
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}
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}
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2018-06-20 07:59:11 -04:00
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return ESP_OK;
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}
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void sdmmc_flip_byte_order(uint32_t* response, size_t size)
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{
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assert(size % (2 * sizeof(uint32_t)) == 0);
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const size_t n_words = size / sizeof(uint32_t);
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for (int i = 0; i < n_words / 2; ++i) {
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uint32_t left = __builtin_bswap32(response[i]);
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uint32_t right = __builtin_bswap32(response[n_words - i - 1]);
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response[i] = right;
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response[n_words - i - 1] = left;
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}
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}
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void sdmmc_card_print_info(FILE* stream, const sdmmc_card_t* card)
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{
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bool print_scr = false;
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bool print_csd = false;
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const char* type;
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2022-07-12 18:00:46 -04:00
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2018-06-20 07:59:11 -04:00
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fprintf(stream, "Name: %s\n", card->cid.name);
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2022-07-12 18:00:46 -04:00
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2018-06-20 07:59:11 -04:00
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if (card->is_sdio) {
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type = "SDIO";
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print_scr = true;
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print_csd = true;
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} else if (card->is_mmc) {
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type = "MMC";
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print_csd = true;
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} else {
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type = (card->ocr & SD_OCR_SDHC_CAP) ? "SDHC/SDXC" : "SDSC";
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2022-02-25 06:44:53 -05:00
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print_csd = true;
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2018-06-20 07:59:11 -04:00
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}
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fprintf(stream, "Type: %s\n", type);
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2022-07-12 18:00:46 -04:00
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if (card->real_freq_khz == 0) {
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fprintf(stream, "Speed: N/A\n");
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2018-08-22 06:16:32 -04:00
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} else {
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2022-07-12 18:00:46 -04:00
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const char *freq_unit = card->real_freq_khz < 1000 ? "kHz" : "MHz";
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const float freq = card->real_freq_khz < 1000 ? card->real_freq_khz : card->real_freq_khz / 1000.0;
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const char *max_freq_unit = card->max_freq_khz < 1000 ? "kHz" : "MHz";
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const float max_freq = card->max_freq_khz < 1000 ? card->max_freq_khz : card->max_freq_khz / 1000.0;
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fprintf(stream, "Speed: %.2f %s (limit: %.2f %s)%s\n", freq, freq_unit, max_freq, max_freq_unit, card->is_ddr ? ", DDR" : "");
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2018-08-22 06:16:32 -04:00
|
|
|
}
|
2022-07-12 18:00:46 -04:00
|
|
|
|
2018-06-20 07:59:11 -04:00
|
|
|
fprintf(stream, "Size: %lluMB\n", ((uint64_t) card->csd.capacity) * card->csd.sector_size / (1024 * 1024));
|
|
|
|
|
|
|
|
if (print_csd) {
|
|
|
|
fprintf(stream, "CSD: ver=%d, sector_size=%d, capacity=%d read_bl_len=%d\n",
|
2023-10-17 10:13:32 -04:00
|
|
|
(int) (card->is_mmc ? card->csd.csd_ver : card->csd.csd_ver + 1),
|
2018-06-20 07:59:11 -04:00
|
|
|
card->csd.sector_size, card->csd.capacity, card->csd.read_block_len);
|
2022-02-25 06:44:53 -05:00
|
|
|
if (card->is_mmc) {
|
2023-10-17 10:13:32 -04:00
|
|
|
fprintf(stream, "EXT CSD: bus_width=%" PRIu32 "\n", (uint32_t) (1 << card->log_bus_width));
|
2022-02-25 06:44:53 -05:00
|
|
|
} else if (!card->is_sdio){ // make sure card is SD
|
2023-10-17 10:13:32 -04:00
|
|
|
fprintf(stream, "SSR: bus_width=%" PRIu32 "\n", (uint32_t) (card->ssr.cur_bus_width ? 4 : 1));
|
2022-02-25 06:44:53 -05:00
|
|
|
}
|
2018-06-20 07:59:11 -04:00
|
|
|
}
|
|
|
|
if (print_scr) {
|
|
|
|
fprintf(stream, "SCR: sd_spec=%d, bus_width=%d\n", card->scr.sd_spec, card->scr.bus_width);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t sdmmc_fix_host_flags(sdmmc_card_t* card)
|
|
|
|
{
|
|
|
|
const uint32_t width_1bit = SDMMC_HOST_FLAG_1BIT;
|
|
|
|
const uint32_t width_4bit = SDMMC_HOST_FLAG_4BIT;
|
|
|
|
const uint32_t width_8bit = SDMMC_HOST_FLAG_8BIT;
|
|
|
|
const uint32_t width_mask = width_1bit | width_4bit | width_8bit;
|
|
|
|
|
|
|
|
int slot_bit_width = card->host.get_bus_width(card->host.slot);
|
|
|
|
if (slot_bit_width == 1 &&
|
|
|
|
(card->host.flags & (width_4bit | width_8bit))) {
|
|
|
|
card->host.flags &= ~width_mask;
|
2018-08-22 06:16:32 -04:00
|
|
|
card->host.flags |= width_1bit;
|
|
|
|
} else if (slot_bit_width == 4 && (card->host.flags & width_8bit)) {
|
|
|
|
if ((card->host.flags & width_4bit) == 0) {
|
|
|
|
ESP_LOGW(TAG, "slot width set to 4, but host flags don't have 4 line mode enabled; using 1 line mode");
|
|
|
|
card->host.flags &= ~width_mask;
|
|
|
|
card->host.flags |= width_1bit;
|
|
|
|
} else {
|
|
|
|
card->host.flags &= ~width_mask;
|
|
|
|
card->host.flags |= width_4bit;
|
|
|
|
}
|
2018-06-20 07:59:11 -04:00
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
2022-05-30 09:37:40 -04:00
|
|
|
|
2024-01-01 13:57:13 -05:00
|
|
|
esp_err_t sdmmc_allocate_aligned_buf(sdmmc_card_t* card)
|
|
|
|
{
|
|
|
|
if (card->host.flags & SDMMC_HOST_FLAG_ALLOC_ALIGNED_BUF) {
|
|
|
|
void* buf = NULL;
|
|
|
|
size_t actual_size = 0;
|
|
|
|
esp_err_t ret = esp_dma_malloc(SDMMC_IO_BLOCK_SIZE, 0, &buf, &actual_size);
|
|
|
|
if (ret != ESP_OK) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
assert(actual_size == SDMMC_IO_BLOCK_SIZE);
|
|
|
|
card->host.dma_aligned_buffer = buf;
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2022-05-30 09:37:40 -04:00
|
|
|
uint32_t sdmmc_get_erase_timeout_ms(const sdmmc_card_t* card, int arg, size_t erase_size_kb)
|
|
|
|
{
|
|
|
|
if (card->is_mmc) {
|
|
|
|
return sdmmc_mmc_get_erase_timeout_ms(card, arg, erase_size_kb);
|
|
|
|
} else {
|
|
|
|
return sdmmc_sd_get_erase_timeout_ms(card, arg, erase_size_kb);
|
|
|
|
}
|
|
|
|
}
|