alex/esp-idf
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esp-idf/components/spi_flash/CMakeLists.txt

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CMake
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build system: Initial cmake support, work in progress
2018-01-11 21:49:13 -05:00
if(BOOTLOADER_BUILD)
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-21 22:51:49 -04:00
if (CONFIG_IDF_TARGET_ESP32)
# ESP32 Bootloader needs SPIUnlock from this file, but doesn't
# need other parts of this component
fix dummy issue in spi mem and make some spiflash api called from idf
2019-11-05 00:10:03 -05:00
set(srcs "esp32/spi_flash_rom_patch.c")
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-21 22:51:49 -04:00
else()
# but on other platforms no source files are needed for bootloader
set(srcs)
endif()
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 01:11:36 -04:00
set(cache_srcs "")
bootloader: fix the WRSR format for ISSI flash chips 1. The 2nd bootloader always call `rom_spiflash_unlock()`, but never help to clear the WEL bit when exit. This may cause system unstability. This commit helps to clear WEL when flash configuration is done. **RISK:** When the app starts, it didn't have to clear the WEL before it actually write/erase. But now the very first write/erase operation should be done after a WEL clear. Though the risk is little (all the following write/erase also need to clear the WEL), we still have to test this carefully, especially for those functions used by the OTA. 2. The `rom_spiflash_unlock()` function in the patch of ESP32 may (1) trigger the QPI, (2) clear the QE or (3) fail to unlock the ISSI chips. Status register bitmap of ISSI chip and GD chip: | SR | ISSI | GD25LQ32C | | -- | ---- | --------- | | 0 | WIP | WIP | | 1 | WEL | WEL | | 2 | BP0 | BP0 | | 3 | BP1 | BP1 | | 4 | BP2 | BP2 | | 5 | BP3 | BP3 | | 6 | QE | BP4 | | 7 | SRWD | SRP0 | | 8 | | SRP1 | | 9 | | QE | | 10 | | SUS2 | | 11 | | LB1 | | 12 | | LB2 | | 13 | | LB3 | | 14 | | CMP | | 15 | | SUS1 | QE bit of other chips are at the bit 9 of the status register (i.e. bit 1 of SR2), which should be read by RDSR2 command. However, the RDSR2 (35H, Read Status 2) command for chip of other vendors happens to be the QIOEN (Enter QPI mode) command of ISSI chips. When the `rom_spiflash_unlock()` function trys to read SR2, it may trigger the QPI of ISSI chips. Moreover, when `rom_spiflash_unlock()` try to clear the BP4 bit in the status register, QE (bit 6) of ISSI chip may be cleared by accident. Or if the ISSI chip doesn't accept WRSR command with argument of two bytes (since it only have status register of one byte), it may fail to clear the other protect bits (BP0~BP3) as expected. This commit makes the `rom_spiflash_unlock()` check whether the vendor is issi. if so, `rom_spiflash_unlock()` only send RDSR to read the status register, send WRSR with only 1 byte argument, and also avoid clearing the QE bit (bit 6). 3. `rom_spiflash_unlock()` always send WRSR command to clear protection bits even when there is no protection bit active. And the execution of clearing status registers, which takes about 700us, will also happen even when there's no bits cleared. This commit skips the clearing of status register if there is no protection bits active. Also move the execute_flash_command to be a bootloader API; move implementation of spi_flash_wrap_set to the bootloader
2020-03-12 06:20:31 -04:00
set(priv_requires bootloader_support soc)
build system: Initial cmake support, work in progress
2018-01-11 21:49:13 -05:00
else()
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 01:11:36 -04:00
set(cache_srcs
cmake: some formatting fixes Do not include bootloader in flash target when secure boot is enabled. Emit signing warning on all cases where signed apps are enabled (secure boot and signed images) Follow convention of capital letters for SECURE_BOOT_SIGNING_KEY variable, since it is relevant to other components, not just bootloader. Pass signing key and verification key via config, not requiring bootloader to know parent app dir. Misc. variables name corrections
2019-06-21 02:29:32 -04:00
"cache_utils.c"
"flash_mmap.c"
"flash_ops.c"
spi_flash: Use per-chip flash_ops files for legacy API Looks like when ESP32-S2 Beta support was merged, the separate files were dropped by accident.
2020-04-16 07:31:13 -04:00
"${IDF_TARGET}/flash_ops_${IDF_TARGET}.c"
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 01:11:36 -04:00
)
set(srcs
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-21 22:51:49 -04:00
"partition.c")
if (CONFIG_IDF_TARGET_ESP32)
list(APPEND srcs
fix dummy issue in spi mem and make some spiflash api called from idf
2019-11-05 00:10:03 -05:00
"esp32/spi_flash_rom_patch.c")
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-21 22:51:49 -04:00
endif()
esp_flash: fix the quad issue for some GD flash chips The GD flash with product ID 40H, is already used in Wrover-nosufix modules.
2019-09-09 12:56:46 -04:00
# New implementation after IDF v4.0
esp_flash: fix coredump for legacy spi flash API When legacy mode is used, the coredump still fails during linking because "esp_flash_init_default_chip", "esp_flash_app_init" and "esp_flash_default_chip " are not compiled and linked. Instead of using ``if`` macros in callers, these functions are protected by ``if`` macros in the header, and also not compiled in the sources. "esp_flash_default_chip" variable is compiled with safe default value.
2019-09-10 02:34:06 -04:00
list(APPEND srcs
cmake: some formatting fixes Do not include bootloader in flash target when secure boot is enabled. Emit signing warning on all cases where signed apps are enabled (secure boot and signed images) Follow convention of capital letters for SECURE_BOOT_SIGNING_KEY variable, since it is relevant to other components, not just bootloader. Pass signing key and verification key via config, not requiring bootloader to know parent app dir. Misc. variables name corrections
2019-06-21 02:29:32 -04:00
"spi_flash_chip_drivers.c"
"spi_flash_chip_generic.c"
"spi_flash_chip_issi.c"
esp_flash: support MXIC flash chips The default chip driver (chip_generic) use command 01H + 2 bytes to clear the QE bit. However this will accidently change the configuration register value of the MXIC chip. MXIC chip driver is added to fix that.
2020-03-19 10:49:25 -04:00
"spi_flash_chip_mxic.c"
ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation Otherwise IRAM usage is too high in this example.
2019-11-27 20:20:00 -05:00
"spi_flash_chip_gd.c"
"memspi_host_driver.c")
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-21 22:51:49 -04:00
ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation Otherwise IRAM usage is too high in this example.
2019-11-27 20:20:00 -05:00
list(APPEND cache_srcs
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-21 22:51:49 -04:00
"esp_flash_api.c"
"esp_flash_spi_init.c"
"spi_flash_os_func_app.c"
"spi_flash_os_func_noos.c")
ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation Otherwise IRAM usage is too high in this example.
2019-11-27 20:20:00 -05:00
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 01:11:36 -04:00
list(APPEND srcs ${cache_srcs})
esp_ipc: Move to new component This commit moves esp_ipc into a separate component.
2020-04-27 02:29:54 -04:00
set(priv_requires bootloader_support app_update soc esp_ipc)
build system: Initial cmake support, work in progress
2018-01-11 21:49:13 -05:00
endif()
components: use new component registration api
2019-04-28 03:38:23 -04:00
idf_component_register(SRCS "${srcs}"
hal: extract hal component from soc component
2020-08-08 08:15:27 -04:00
REQUIRES hal
components: use new component registration api
2019-04-28 03:38:23 -04:00
PRIV_REQUIRES "${priv_requires}"
INCLUDE_DIRS include
PRIV_INCLUDE_DIRS private_include
LDFRAGMENTS linker.lf)
tools: implement linker script generation
2018-04-17 22:57:45 -04:00
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 01:11:36 -04:00
# Avoid cache miss by unexpected inlineing when built by -Os
set_source_files_properties(${cache_srcs} PROPERTIES COMPILE_FLAGS
"-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once")
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