2021-05-23 20:09:38 -04:00
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2018-07-04 19:01:03 -04:00
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#pragma once
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#include <stdint.h>
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#include <stddef.h>
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#include "esp_err.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/queue.h"
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2018-09-03 11:55:22 -04:00
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#include "driver/sdspi_host.h"
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2018-07-04 19:01:03 -04:00
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/// Control tokens used to frame data transfers
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/// (see section 7.3.3 of SD simplified spec)
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/// Token sent before single/multi block reads and single block writes
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#define TOKEN_BLOCK_START 0b11111110
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/// Token sent before multi block writes
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#define TOKEN_BLOCK_START_WRITE_MULTI 0b11111100
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/// Token used to stop multi block write (for reads, CMD12 is used instead)
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#define TOKEN_BLOCK_STOP_WRITE_MULTI 0b11111101
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/// Data response tokens
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/// Mask (high 3 bits are undefined for data response tokens)
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#define TOKEN_RSP_MASK 0b11111
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/// Data accepted
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#define TOKEN_RSP_OK 0b00101
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/// Data rejected due to CRC error
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#define TOKEN_RSP_CRC_ERR 0b01011
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/// Data rejected due to write error
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#define TOKEN_RSP_WRITE_ERR 0b01101
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/// Data error tokens have format 0b0000xyzw where xyzw are signle bit flags.
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/// MASK and VAL are used to check if a token is an error token
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#define TOKEN_ERR_MASK 0b11110000
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#define TOKEN_ERR_VAL 0b00000000
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/// Argument is out of range
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#define TOKEN_ERR_RANGE BIT(3)
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/// Card internal ECC error
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#define TOKEN_ERR_CARD_ECC BIT(2)
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/// Card controller error
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#define TOKEN_ERR_INTERNAL BIT(1)
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/// Card is locked
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#define TOKEN_ERR_LOCKED BIT(0)
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/// Transfer format in SPI mode. See section 7.3.1.1 of SD simplified spec.
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typedef struct {
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// These fields form the command sent from host to the card (6 bytes)
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uint8_t cmd_index : 6;
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uint8_t transmission_bit : 1;
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uint8_t start_bit : 1;
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uint8_t arguments[4];
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uint8_t stop_bit : 1;
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uint8_t crc7 : 7;
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/// Ncr is the dead time between command and response; should be 0xff
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uint8_t ncr;
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/// Response data, should be set by host to 0xff for read operations
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uint8_t r1;
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/// Up to 16 bytes of response. Luckily, this is aligned on 4 byte boundary.
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uint32_t response[4];
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/// response timeout, in milliseconds
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int timeout_ms;
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} sdspi_hw_cmd_t;
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2018-12-28 13:04:37 -05:00
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#define SDSPI_CMD_SIZE 6
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#define SDSPI_NCR_MIN_SIZE 1
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#define SDSPI_NCR_MAX_SIZE 8
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//the size here contains 6 bytes of CMD, 1 bytes of dummy and the actual response
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#define SDSPI_CMD_NORESP_SIZE (SDSPI_CMD_SIZE+0) //!< Size of the command without any response
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#define SDSPI_CMD_R1_SIZE (SDSPI_CMD_SIZE+SDSPI_NCR_MIN_SIZE+1) //!< Size of the command with R1 response
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#define SDSPI_CMD_R2_SIZE (SDSPI_CMD_SIZE+SDSPI_NCR_MIN_SIZE+2) //!< Size of the command with R1b response
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#define SDSPI_CMD_R3_SIZE (SDSPI_CMD_SIZE+SDSPI_NCR_MIN_SIZE+5) //!< Size of the command with R3 response
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#define SDSPI_CMD_R4_SIZE (SDSPI_CMD_SIZE+SDSPI_NCR_MIN_SIZE+5) //!< Size of the command with R4 response
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#define SDSPI_CMD_R5_SIZE (SDSPI_CMD_SIZE+SDSPI_NCR_MIN_SIZE+2) //!< Size of the command with R5 response
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#define SDSPI_CMD_R7_SIZE (SDSPI_CMD_SIZE+SDSPI_NCR_MIN_SIZE+5) //!< Size of the command with R7 response
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2018-07-04 19:01:03 -04:00
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#define SDSPI_CMD_FLAG_DATA BIT(0) //!< Command has data transfer
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#define SDSPI_CMD_FLAG_WRITE BIT(1) //!< Data is written to the card
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#define SDSPI_CMD_FLAG_RSP_R1 BIT(2) //!< Response format R1 (1 byte)
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2022-04-10 15:45:01 -04:00
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#define SDSPI_CMD_FLAG_RSP_R1B BIT(3) //!< Response format R1 (1 byte), with busy polling
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#define SDSPI_CMD_FLAG_RSP_R2 BIT(4) //!< Response format R2 (2 bytes)
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#define SDSPI_CMD_FLAG_RSP_R3 BIT(5) //!< Response format R3 (5 bytes)
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#define SDSPI_CMD_FLAG_RSP_R4 BIT(6) //!< Response format R4 (5 bytes)
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#define SDSPI_CMD_FLAG_RSP_R5 BIT(7) //!< Response format R5 (2 bytes)
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#define SDSPI_CMD_FLAG_RSP_R7 BIT(8) //!< Response format R7 (5 bytes)
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#define SDSPI_CMD_FLAG_NORSP BIT(9) //!< Don't expect response (used when sending CMD0 first time).
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#define SDSPI_CMD_FLAG_MULTI_BLK BIT(10) //!< For the write multiblock commands, the start token should be different
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2018-07-04 19:01:03 -04:00
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#define SDSPI_MAX_DATA_LEN 512 //!< Max size of single block transfer
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void make_hw_cmd(uint32_t opcode, uint32_t arg, int timeout_ms, sdspi_hw_cmd_t *hw_cmd);
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2018-09-03 11:55:22 -04:00
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esp_err_t sdspi_host_start_command(sdspi_dev_handle_t handle, sdspi_hw_cmd_t *cmd,
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2018-07-04 19:01:03 -04:00
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void *data, uint32_t data_size, int flags);
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