mirror of
https://github.com/espressif/esp-idf.git
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179 lines
8.6 KiB
C
179 lines
8.6 KiB
C
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// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_efuse_utility.h"
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#include "soc/efuse_periph.h"
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#include "esp32s2beta/clk.h"
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#include "esp_log.h"
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#include "assert.h"
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#include "sdkconfig.h"
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#include <sys/param.h>
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#include "esp32s2beta/rom/efuse.h"
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static const char *TAG = "efuse";
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#ifdef CONFIG_EFUSE_VIRTUAL
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extern uint32_t virt_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK];
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#endif // CONFIG_EFUSE_VIRTUAL
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/*Range addresses to read blocks*/
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const esp_efuse_range_addr_t range_read_addr_blocks[] = {
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{EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT
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{EFUSE_RD_MAC_SPI_8M_0_REG, EFUSE_RD_MAC_SPI_8M_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M
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{EFUSE_RD_SYS_DATA0_REG, EFUSE_RD_SYS_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA
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{EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA
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{EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0
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{EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1
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{EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2
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{EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3
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{EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4
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{EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5
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{EFUSE_RD_KEY6_DATA0_REG, EFUSE_RD_KEY6_DATA7_REG} // range address of EFUSE_BLK10 KEY6
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};
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static uint32_t write_mass_blocks[COUNT_EFUSE_BLOCKS][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
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/*Range addresses to write blocks (it is not real regs, it is buffer) */
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const esp_efuse_range_addr_t range_write_addr_blocks[] = {
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{(uint32_t)&write_mass_blocks[EFUSE_BLK0][0], (uint32_t)&write_mass_blocks[EFUSE_BLK0][5]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK1][0], (uint32_t)&write_mass_blocks[EFUSE_BLK1][5]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK2][0], (uint32_t)&write_mass_blocks[EFUSE_BLK2][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK3][0], (uint32_t)&write_mass_blocks[EFUSE_BLK3][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK4][0], (uint32_t)&write_mass_blocks[EFUSE_BLK4][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK5][0], (uint32_t)&write_mass_blocks[EFUSE_BLK5][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK6][0], (uint32_t)&write_mass_blocks[EFUSE_BLK6][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK7][0], (uint32_t)&write_mass_blocks[EFUSE_BLK7][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK8][0], (uint32_t)&write_mass_blocks[EFUSE_BLK8][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK9][0], (uint32_t)&write_mass_blocks[EFUSE_BLK9][7]},
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{(uint32_t)&write_mass_blocks[EFUSE_BLK10][0], (uint32_t)&write_mass_blocks[EFUSE_BLK10][7]},
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};
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#ifndef CONFIG_EFUSE_VIRTUAL
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// Update Efuse timing configuration
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static esp_err_t esp_efuse_set_timing(void)
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{
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uint32_t clock = esp_clk_apb_freq();
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// ets_efuse_set_timing(clock);
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uint32_t clk_div, power_on;
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//uint32_t power_off; // Support for 7.2.3 chip
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uint32_t tsup_a = 1, thp_a = 1, tpgm, tpgm_inact;
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uint32_t tsur_a = 1, thr_a = 1, trd;
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if (clock == 20000000 || clock == 5000000 || clock == 10000000) {
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clk_div = 0x28;
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power_on = 0x2880;
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//power_off = 0x40;
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tpgm = 0xc8;
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tpgm_inact = 1;
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trd = 1;
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} else if (clock == 40000000) {
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clk_div = 0x50;
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power_on = 0x5100;
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//power_off = 0x80;
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tpgm = 0x190;
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tpgm_inact = 2;
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trd = 2;
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} else if (clock == 80000000) {
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clk_div = 0xa0;
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power_on = 0xa200;
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//power_off = 0x100;
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tpgm = 0x320;
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tpgm_inact = 3;
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trd = 3;
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} else {
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ESP_LOGE(TAG, "Efuse does not support this %d Hz APB clock", clock);
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return ESP_ERR_NOT_SUPPORTED;
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}
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REG_SET_FIELD(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV, clk_div);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM, tpgm);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_TPGM_INACTIVE, tpgm_inact);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF0_REG, EFUSE_THP_A, thp_a);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_PWR_ON_NUM, power_on);
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REG_SET_FIELD(EFUSE_WR_TIM_CONF1_REG, EFUSE_TSUP_A, tsup_a);
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//REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, power_off);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TSUR_A, tsur_a);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_TRD, trd);
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REG_SET_FIELD(EFUSE_RD_TIM_CONF_REG, EFUSE_THR_A, thr_a);
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return ESP_OK;
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}
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#endif // ifndef CONFIG_EFUSE_VIRTUAL
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// Efuse read operation: copies data from physical efuses to efuse read registers.
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void esp_efuse_utility_clear_program_registers(void)
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{
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ets_efuse_read();
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ets_efuse_clear_program_registers();
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}
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// Burn values written to the efuse write registers
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void esp_efuse_utility_burn_efuses(void)
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{
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#ifdef CONFIG_EFUSE_VIRTUAL
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ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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int subblock = 0;
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
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}
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}
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#else
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if (esp_efuse_set_timing() != ESP_OK) {
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ESP_LOGE(TAG, "Efuse fields are not burnt");
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} else {
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// Permanently update values written to the efuse write registers
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for (int num_block = 0; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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if (REG_READ(addr_wr_block) != 0) {
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if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
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uint8_t block_rs[12];
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ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
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memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
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}
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int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
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memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
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ets_efuse_program(num_block);
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break;
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}
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}
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}
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}
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#endif // CONFIG_EFUSE_VIRTUAL
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esp_efuse_utility_reset();
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}
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// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
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// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
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// The RS coding scheme does not require data changes for the encoded data. esp32s2beta has special registers for this.
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// They will be filled during the burn operation.
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esp_err_t esp_efuse_utility_apply_new_coding_scheme()
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{
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// start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
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for (int num_block = 1; num_block < COUNT_EFUSE_BLOCKS; num_block++) {
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if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
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for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
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if (REG_READ(addr_wr_block)) {
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int num_reg = 0;
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for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
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if (esp_efuse_utility_read_reg(num_block, num_reg)) {
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ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
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return ESP_ERR_CODING;
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}
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}
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break;
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}
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}
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}
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}
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return ESP_OK;
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}
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