esp-idf/examples/system/ulp_riscv/gpio/CMakeLists.txt

# The following lines of boilerplate have to be in your project's CMakeLists
# in this exact order for cmake to work correctly
cmake_minimum_required(VERSION 3.16)

if(NOT IDF_TARGET STREQUAL "esp32s2")
    #IDF-4514
    message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")
    return()
endif()

include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(ulp_riscv_example)
ulp: added support to building code for riscv ULP coprocessor 2020-04-17 15:34:56 -04:00			`# The following lines of boilerplate have to be in your project's CMakeLists`
			`# in this exact order for cmake to work correctly`
tools: Increase the minimal supported CMake version to 3.16 This updates the minimal supported version of CMake to 3.16, which in turn enables us to use more CMake features and have a cleaner build system. This is the version that provides most new features and also the one we use in our latest docker image for CI. 2022-05-27 04:10:51 -04:00			`cmake_minimum_required(VERSION 3.16)`
ulp: added support to building code for riscv ULP coprocessor 2020-04-17 15:34:56 -04:00
ulp: Added ULP RISC-V support for esp32s3 This commit adds support for ULP RISC-V for esp32s3. Signed-off-by: Sudeep Mohanty <sudeep.mohanty@espressif.com> 2021-12-23 01:12:47 -05:00			`if(NOT IDF_TARGET STREQUAL "esp32s2")`
			`#IDF-4514`
			`message(FATAL_ERROR "DO NOT BUILD THIS APP FOR ANY TARGET OTHER THAN ESP32-S2 OTHERWISE YOU MAY BRICK YOUR DEVICE")`
			`return()`
			`endif()`

ulp: added support to building code for riscv ULP coprocessor 2020-04-17 15:34:56 -04:00			`include($ENV{IDF_PATH}/tools/cmake/project.cmake)`
[examples]: removed hyphens Replaced hyphens with underscores in examples project definition for all examples which had hyphens in their project name. dpp-enrollee is an exceptions because the name matches the project directory name while the project directory also contains hyphens. 2021-07-05 02:33:56 -04:00			`project(ulp_riscv_example)`