2021-05-23 20:09:38 -04:00
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2019-07-15 02:44:15 -04:00
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2016-10-08 02:12:55 -04:00
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#include <esp_types.h>
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#include "esp_err.h"
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#include "freertos/FreeRTOS.h"
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#include "driver/gpio.h"
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2016-12-07 01:18:10 -05:00
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#include "driver/rtc_io.h"
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2016-10-08 02:12:55 -04:00
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#include "soc/soc.h"
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2019-06-10 00:08:08 -04:00
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#include "soc/periph_defs.h"
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2019-08-15 03:05:59 -04:00
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#if !CONFIG_FREERTOS_UNICORE
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2019-07-17 23:34:49 -04:00
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#include "esp_ipc.h"
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2019-08-15 03:05:59 -04:00
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#endif
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2016-10-08 02:12:55 -04:00
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2020-09-09 22:37:58 -04:00
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#include "soc/soc_caps.h"
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2019-07-15 02:44:15 -04:00
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#include "soc/gpio_periph.h"
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#include "esp_log.h"
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2021-08-25 05:02:19 -04:00
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#include "esp_check.h"
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2019-07-15 02:44:15 -04:00
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#include "hal/gpio_hal.h"
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2020-06-19 00:00:58 -04:00
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#include "esp_rom_gpio.h"
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2019-07-15 02:44:15 -04:00
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static const char *GPIO_TAG = "gpio";
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2021-08-25 05:02:19 -04:00
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#define GPIO_CHECK(a, str, ret_val) ESP_RETURN_ON_FALSE(a, ret_val, GPIO_TAG, "%s", str)
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2020-09-12 05:58:30 -04:00
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2019-07-17 23:34:49 -04:00
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#define GPIO_ISR_CORE_ID_UNINIT (3)
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2016-10-08 02:12:55 -04:00
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2020-09-12 05:58:30 -04:00
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//default value for SOC_GPIO_SUPPORT_RTC_INDEPENDENT is 0
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#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0
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#endif
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2016-12-24 07:45:57 -05:00
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typedef struct {
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gpio_isr_t fn; /*!< isr function */
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2019-07-15 02:44:15 -04:00
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void *args; /*!< isr function args */
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2016-12-24 07:45:57 -05:00
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} gpio_isr_func_t;
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2019-07-17 23:34:49 -04:00
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// Used by the IPC call to register the interrupt service routine.
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typedef struct {
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int source; /*!< ISR source */
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int intr_alloc_flags; /*!< ISR alloc flag */
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void (*fn)(void*); /*!< ISR function */
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void *arg; /*!< ISR function args*/
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void *handle; /*!< ISR handle */
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esp_err_t ret;
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} gpio_isr_alloc_t;
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2019-07-15 02:44:15 -04:00
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typedef struct {
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gpio_hal_context_t *gpio_hal;
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portMUX_TYPE gpio_spinlock;
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uint32_t isr_core_id;
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gpio_isr_func_t *gpio_isr_func;
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gpio_isr_handle_t gpio_isr_handle;
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2022-08-24 05:06:20 -04:00
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uint64_t isr_clr_on_entry_mask; // for edge-triggered interrupts, interrupt status bits should be cleared before entering per-pin handlers
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2019-07-15 02:44:15 -04:00
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} gpio_context_t;
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static gpio_hal_context_t _gpio_hal = {
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.dev = GPIO_HAL_GET_HW(GPIO_PORT_0)
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};
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static gpio_context_t gpio_context = {
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.gpio_hal = &_gpio_hal,
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.gpio_spinlock = portMUX_INITIALIZER_UNLOCKED,
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.isr_core_id = GPIO_ISR_CORE_ID_UNINIT,
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.gpio_isr_func = NULL,
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2022-08-24 05:06:20 -04:00
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.isr_clr_on_entry_mask = 0,
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2019-07-15 02:44:15 -04:00
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};
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2016-12-24 07:45:57 -05:00
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esp_err_t gpio_pullup_en(gpio_num_t gpio_num)
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{
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2016-11-14 21:29:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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2020-09-09 22:37:58 -04:00
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if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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2019-07-15 02:44:15 -04:00
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portENTER_CRITICAL(&gpio_context.gpio_spinlock);
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gpio_hal_pullup_en(gpio_context.gpio_hal, gpio_num);
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portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
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2019-11-26 07:00:24 -05:00
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} else {
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2020-11-26 03:56:13 -05:00
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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2019-11-26 07:00:24 -05:00
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rtc_gpio_pullup_en(gpio_num);
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2020-11-26 03:56:13 -05:00
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#else
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abort(); // This should be eliminated as unreachable, unless a programming error has occured
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#endif
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2016-12-07 01:18:10 -05:00
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}
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2019-07-15 02:44:15 -04:00
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2016-11-14 21:29:52 -05:00
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return ESP_OK;
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}
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2016-12-24 07:45:57 -05:00
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esp_err_t gpio_pullup_dis(gpio_num_t gpio_num)
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{
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2016-11-14 21:29:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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2020-09-09 22:37:58 -04:00
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if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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2019-07-15 02:44:15 -04:00
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portENTER_CRITICAL(&gpio_context.gpio_spinlock);
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gpio_hal_pullup_dis(gpio_context.gpio_hal, gpio_num);
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portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
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2019-11-26 07:00:24 -05:00
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} else {
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2020-11-26 03:56:13 -05:00
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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2019-11-26 07:00:24 -05:00
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rtc_gpio_pullup_dis(gpio_num);
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2020-11-26 03:56:13 -05:00
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#else
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abort(); // This should be eliminated as unreachable, unless a programming error has occured
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#endif
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2016-12-07 01:18:10 -05:00
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}
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2019-07-15 02:44:15 -04:00
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2016-11-14 21:29:52 -05:00
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return ESP_OK;
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}
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2016-12-24 07:45:57 -05:00
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esp_err_t gpio_pulldown_en(gpio_num_t gpio_num)
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{
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2016-11-14 21:29:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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2020-09-09 22:37:58 -04:00
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if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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2019-07-15 02:44:15 -04:00
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portENTER_CRITICAL(&gpio_context.gpio_spinlock);
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gpio_hal_pulldown_en(gpio_context.gpio_hal, gpio_num);
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portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
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2019-11-26 07:00:24 -05:00
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} else {
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2020-11-26 03:56:13 -05:00
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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2019-11-26 07:00:24 -05:00
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rtc_gpio_pulldown_en(gpio_num);
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2020-11-26 03:56:13 -05:00
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#else
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abort(); // This should be eliminated as unreachable, unless a programming error has occured
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#endif
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2016-12-07 01:18:10 -05:00
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}
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2019-07-15 02:44:15 -04:00
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2016-11-14 21:29:52 -05:00
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return ESP_OK;
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}
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2016-12-24 07:45:57 -05:00
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esp_err_t gpio_pulldown_dis(gpio_num_t gpio_num)
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{
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2016-11-14 21:29:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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2020-09-09 22:37:58 -04:00
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if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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2019-07-15 02:44:15 -04:00
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portENTER_CRITICAL(&gpio_context.gpio_spinlock);
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gpio_hal_pulldown_dis(gpio_context.gpio_hal, gpio_num);
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portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
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2019-11-26 07:00:24 -05:00
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} else {
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2020-11-26 03:56:13 -05:00
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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2019-11-26 07:00:24 -05:00
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rtc_gpio_pulldown_dis(gpio_num);
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2020-11-26 03:56:13 -05:00
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#else
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abort(); // This should be eliminated as unreachable, unless a programming error has occured
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#endif
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2016-12-07 01:18:10 -05:00
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}
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2019-07-15 02:44:15 -04:00
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2016-11-14 21:29:52 -05:00
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return ESP_OK;
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}
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2016-12-24 07:45:57 -05:00
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2016-10-08 02:12:55 -04:00
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esp_err_t gpio_set_intr_type(gpio_num_t gpio_num, gpio_int_type_t intr_type)
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{
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2016-11-07 01:16:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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GPIO_CHECK(intr_type < GPIO_INTR_MAX, "GPIO interrupt type error", ESP_ERR_INVALID_ARG);
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2016-10-08 02:12:55 -04:00
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2019-07-15 02:44:15 -04:00
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portENTER_CRITICAL(&gpio_context.gpio_spinlock);
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gpio_hal_set_intr_type(gpio_context.gpio_hal, gpio_num, intr_type);
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2022-08-24 05:06:20 -04:00
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if (intr_type == GPIO_INTR_POSEDGE || intr_type == GPIO_INTR_NEGEDGE || intr_type == GPIO_INTR_ANYEDGE) {
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gpio_context.isr_clr_on_entry_mask |= (1ULL << (gpio_num));
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} else {
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gpio_context.isr_clr_on_entry_mask &= ~(1ULL << (gpio_num));
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}
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2019-07-15 02:44:15 -04:00
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portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
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return ESP_OK;
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2018-06-03 22:34:23 -04:00
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}
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2019-07-15 02:44:15 -04:00
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static esp_err_t gpio_intr_enable_on_core(gpio_num_t gpio_num, uint32_t core_id)
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2016-10-08 02:12:55 -04:00
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{
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2019-07-15 02:44:15 -04:00
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gpio_hal_intr_enable_on_core(gpio_context.gpio_hal, gpio_num, core_id);
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2016-10-08 02:12:55 -04:00
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return ESP_OK;
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}
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2017-01-19 07:46:41 -05:00
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esp_err_t gpio_intr_enable(gpio_num_t gpio_num)
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{
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2019-07-17 23:34:49 -04:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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portENTER_CRITICAL(&gpio_context.gpio_spinlock);
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if(gpio_context.isr_core_id == GPIO_ISR_CORE_ID_UNINIT) {
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gpio_context.isr_core_id = xPortGetCoreID();
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2019-07-17 23:34:49 -04:00
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}
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2019-07-15 02:44:15 -04:00
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portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
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return gpio_intr_enable_on_core (gpio_num, gpio_context.isr_core_id);
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2017-01-19 07:46:41 -05:00
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}
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2016-10-08 02:12:55 -04:00
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esp_err_t gpio_intr_disable(gpio_num_t gpio_num)
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{
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2016-11-07 01:16:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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gpio_hal_intr_disable(gpio_context.gpio_hal, gpio_num);
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2016-10-08 02:12:55 -04:00
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return ESP_OK;
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}
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2019-07-15 02:44:15 -04:00
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static esp_err_t gpio_input_disable(gpio_num_t gpio_num)
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2016-10-08 02:12:55 -04:00
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{
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2016-11-07 01:16:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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gpio_hal_input_disable(gpio_context.gpio_hal, gpio_num);
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return ESP_OK;
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}
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2017-06-25 22:41:40 -04:00
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2019-07-15 02:44:15 -04:00
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static esp_err_t gpio_input_enable(gpio_num_t gpio_num)
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{
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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gpio_hal_input_enable(gpio_context.gpio_hal, gpio_num);
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return ESP_OK;
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}
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2017-06-25 22:41:40 -04:00
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2019-07-15 02:44:15 -04:00
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static esp_err_t gpio_output_disable(gpio_num_t gpio_num)
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{
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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gpio_hal_output_disable(gpio_context.gpio_hal, gpio_num);
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2016-10-08 02:12:55 -04:00
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return ESP_OK;
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}
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static esp_err_t gpio_output_enable(gpio_num_t gpio_num)
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{
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2016-11-07 01:16:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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gpio_hal_output_enable(gpio_context.gpio_hal, gpio_num);
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2020-06-19 00:00:58 -04:00
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esp_rom_gpio_connect_out_signal(gpio_num, SIG_GPIO_OUT_IDX, false, false);
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2016-10-08 02:12:55 -04:00
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return ESP_OK;
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}
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2019-07-15 02:44:15 -04:00
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static esp_err_t gpio_od_disable(gpio_num_t gpio_num)
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{
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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gpio_hal_od_disable(gpio_context.gpio_hal, gpio_num);
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return ESP_OK;
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}
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static esp_err_t gpio_od_enable(gpio_num_t gpio_num)
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{
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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gpio_hal_od_enable(gpio_context.gpio_hal, gpio_num);
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return ESP_OK;
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}
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2016-10-08 02:12:55 -04:00
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esp_err_t gpio_set_level(gpio_num_t gpio_num, uint32_t level)
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{
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2016-12-21 21:05:19 -05:00
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GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
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2019-07-15 02:44:15 -04:00
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gpio_hal_set_level(gpio_context.gpio_hal, gpio_num, level);
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2016-10-08 02:12:55 -04:00
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return ESP_OK;
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}
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int gpio_get_level(gpio_num_t gpio_num)
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{
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2019-07-15 02:44:15 -04:00
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return gpio_hal_get_level(gpio_context.gpio_hal, gpio_num);
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2016-10-08 02:12:55 -04:00
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}
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esp_err_t gpio_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
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{
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2016-11-07 01:16:52 -05:00
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GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
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GPIO_CHECK(pull <= GPIO_FLOATING, "GPIO pull mode error", ESP_ERR_INVALID_ARG);
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2016-10-08 02:12:55 -04:00
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esp_err_t ret = ESP_OK;
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2019-07-15 02:44:15 -04:00
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2016-12-07 01:18:10 -05:00
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switch (pull) {
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2019-07-15 02:44:15 -04:00
|
|
|
case GPIO_PULLUP_ONLY:
|
|
|
|
gpio_pulldown_dis(gpio_num);
|
|
|
|
gpio_pullup_en(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_PULLDOWN_ONLY:
|
|
|
|
gpio_pulldown_en(gpio_num);
|
|
|
|
gpio_pullup_dis(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_PULLUP_PULLDOWN:
|
|
|
|
gpio_pulldown_en(gpio_num);
|
|
|
|
gpio_pullup_en(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_FLOATING:
|
|
|
|
gpio_pulldown_dis(gpio_num);
|
|
|
|
gpio_pullup_dis(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ESP_LOGE(GPIO_TAG, "Unknown pull up/down mode,gpio_num=%u,pull=%u", gpio_num, pull);
|
|
|
|
ret = ESP_ERR_INVALID_ARG;
|
|
|
|
break;
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-10-08 02:12:55 -04:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
|
|
|
|
{
|
2016-11-07 01:16:52 -05:00
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
2019-07-15 02:44:15 -04:00
|
|
|
|
|
|
|
if ((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) != true) && (mode & GPIO_MODE_DEF_OUTPUT)) {
|
2016-12-07 01:18:10 -05:00
|
|
|
ESP_LOGE(GPIO_TAG, "io_num=%d can only be input", gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-10-08 02:12:55 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if (mode & GPIO_MODE_DEF_INPUT) {
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_input_enable(gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_input_disable(gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if (mode & GPIO_MODE_DEF_OUTPUT) {
|
2017-06-25 22:41:40 -04:00
|
|
|
gpio_output_enable(gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2017-06-25 22:41:40 -04:00
|
|
|
gpio_output_disable(gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if (mode & GPIO_MODE_DEF_OD) {
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_od_enable(gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_od_disable(gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-10-08 02:12:55 -04:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-04-13 13:33:33 -04:00
|
|
|
esp_err_t gpio_config(const gpio_config_t *pGPIOConfig)
|
2016-10-08 02:12:55 -04:00
|
|
|
{
|
|
|
|
uint64_t gpio_pin_mask = (pGPIOConfig->pin_bit_mask);
|
|
|
|
uint32_t io_reg = 0;
|
|
|
|
uint32_t io_num = 0;
|
2016-11-07 01:16:52 -05:00
|
|
|
uint8_t input_en = 0;
|
|
|
|
uint8_t output_en = 0;
|
|
|
|
uint8_t od_en = 0;
|
|
|
|
uint8_t pu_en = 0;
|
|
|
|
uint8_t pd_en = 0;
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2020-09-09 22:37:58 -04:00
|
|
|
if (pGPIOConfig->pin_bit_mask == 0 ||
|
|
|
|
pGPIOConfig->pin_bit_mask & ~SOC_GPIO_VALID_GPIO_MASK) {
|
2016-11-07 01:16:52 -05:00
|
|
|
ESP_LOGE(GPIO_TAG, "GPIO_PIN mask error ");
|
2016-10-08 02:12:55 -04:00
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2020-09-09 22:37:58 -04:00
|
|
|
if (pGPIOConfig->mode & GPIO_MODE_DEF_OUTPUT &&
|
|
|
|
pGPIOConfig->pin_bit_mask & ~SOC_GPIO_VALID_OUTPUT_GPIO_MASK) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "GPIO can only be used as input mode");
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-10-08 02:12:55 -04:00
|
|
|
do {
|
|
|
|
io_reg = GPIO_PIN_MUX_REG[io_num];
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2018-06-03 22:34:23 -04:00
|
|
|
if (((gpio_pin_mask >> io_num) & BIT(0))) {
|
2020-09-09 22:37:58 -04:00
|
|
|
assert(io_reg != (intptr_t)NULL);
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
2019-07-15 02:44:15 -04:00
|
|
|
if (rtc_gpio_is_valid_gpio(io_num)) {
|
2016-12-07 01:18:10 -05:00
|
|
|
rtc_gpio_deinit(io_num);
|
|
|
|
}
|
2020-11-26 03:56:13 -05:00
|
|
|
#endif
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if ((pGPIOConfig->mode) & GPIO_MODE_DEF_INPUT) {
|
2016-11-07 01:16:52 -05:00
|
|
|
input_en = 1;
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_input_enable(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_input_disable(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OD) {
|
2016-11-07 01:16:52 -05:00
|
|
|
od_en = 1;
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_od_enable(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_od_disable(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if ((pGPIOConfig->mode) & GPIO_MODE_DEF_OUTPUT) {
|
2016-11-07 01:16:52 -05:00
|
|
|
output_en = 1;
|
2016-10-08 02:12:55 -04:00
|
|
|
gpio_output_enable(io_num);
|
|
|
|
} else {
|
|
|
|
gpio_output_disable(io_num);
|
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if (pGPIOConfig->pull_up_en) {
|
2016-11-07 01:16:52 -05:00
|
|
|
pu_en = 1;
|
2016-12-07 01:18:10 -05:00
|
|
|
gpio_pullup_en(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2016-12-07 01:18:10 -05:00
|
|
|
gpio_pullup_dis(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if (pGPIOConfig->pull_down_en) {
|
2016-11-07 01:16:52 -05:00
|
|
|
pd_en = 1;
|
2016-12-07 01:18:10 -05:00
|
|
|
gpio_pulldown_en(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2016-12-07 01:18:10 -05:00
|
|
|
gpio_pulldown_dis(io_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2022-08-04 01:08:48 -04:00
|
|
|
ESP_LOGI(GPIO_TAG, "GPIO[%"PRIu32"]| InputEn: %d| OutputEn: %d| OpenDrain: %d| Pullup: %d| Pulldown: %d| Intr:%d ", io_num, input_en, output_en, od_en, pu_en, pd_en, pGPIOConfig->intr_type);
|
2016-10-08 02:12:55 -04:00
|
|
|
gpio_set_intr_type(io_num, pGPIOConfig->intr_type);
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-12-07 01:18:10 -05:00
|
|
|
if (pGPIOConfig->intr_type) {
|
2016-10-08 02:12:55 -04:00
|
|
|
gpio_intr_enable(io_num);
|
|
|
|
} else {
|
|
|
|
gpio_intr_disable(io_num);
|
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2021-02-10 04:22:41 -05:00
|
|
|
/* By default, all the pins have to be configured as GPIO pins. */
|
2021-03-15 22:55:05 -04:00
|
|
|
gpio_hal_iomux_func_sel(io_reg, PIN_FUNC_GPIO);
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-10-08 02:12:55 -04:00
|
|
|
io_num++;
|
2016-12-07 01:18:10 -05:00
|
|
|
} while (io_num < GPIO_PIN_COUNT);
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-10-08 02:12:55 -04:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2018-06-08 03:33:04 -04:00
|
|
|
esp_err_t gpio_reset_pin(gpio_num_t gpio_num)
|
|
|
|
{
|
2022-03-21 09:25:21 -04:00
|
|
|
assert(GPIO_IS_VALID_GPIO(gpio_num));
|
2018-06-08 03:33:04 -04:00
|
|
|
gpio_config_t cfg = {
|
2018-08-08 08:31:17 -04:00
|
|
|
.pin_bit_mask = BIT64(gpio_num),
|
2018-06-08 03:33:04 -04:00
|
|
|
.mode = GPIO_MODE_DISABLE,
|
|
|
|
//for powersave reasons, the GPIO should not be floating, select pullup
|
|
|
|
.pull_up_en = true,
|
|
|
|
.pull_down_en = false,
|
|
|
|
.intr_type = GPIO_INTR_DISABLE,
|
|
|
|
};
|
|
|
|
gpio_config(&cfg);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
static inline void IRAM_ATTR gpio_isr_loop(uint32_t status, const uint32_t gpio_num_start)
|
|
|
|
{
|
2018-12-21 09:07:51 -05:00
|
|
|
while (status) {
|
|
|
|
int nbit = __builtin_ffs(status) - 1;
|
|
|
|
status &= ~(1 << nbit);
|
|
|
|
int gpio_num = gpio_num_start + nbit;
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2022-08-24 05:06:20 -04:00
|
|
|
bool intr_status_bit_cleared = false;
|
|
|
|
// Edge-triggered type interrupt can clear the interrupt status bit before entering per-pin interrupt handler
|
|
|
|
if ((1ULL << (gpio_num)) & gpio_context.isr_clr_on_entry_mask) {
|
|
|
|
intr_status_bit_cleared = true;
|
|
|
|
gpio_hal_clear_intr_status_bit(gpio_context.gpio_hal, gpio_num);
|
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
if (gpio_context.gpio_isr_func[gpio_num].fn != NULL) {
|
|
|
|
gpio_context.gpio_isr_func[gpio_num].fn(gpio_context.gpio_isr_func[gpio_num].args);
|
2018-12-21 09:07:51 -05:00
|
|
|
}
|
2022-08-24 05:06:20 -04:00
|
|
|
|
|
|
|
// If the interrupt status bit was not cleared at the entry, then must clear it before exiting
|
|
|
|
if (!intr_status_bit_cleared) {
|
|
|
|
gpio_hal_clear_intr_status_bit(gpio_context.gpio_hal, gpio_num);
|
|
|
|
}
|
2018-12-21 09:07:51 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
static void IRAM_ATTR gpio_intr_service(void *arg)
|
2016-12-24 07:45:57 -05:00
|
|
|
{
|
|
|
|
//GPIO intr process
|
2019-07-15 02:44:15 -04:00
|
|
|
if (gpio_context.gpio_isr_func == NULL) {
|
2016-12-24 07:45:57 -05:00
|
|
|
return;
|
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2018-12-21 09:07:51 -05:00
|
|
|
//read status to get interrupt status for GPIO0-31
|
2019-08-08 00:00:45 -04:00
|
|
|
uint32_t gpio_intr_status;
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_hal_get_intr_status(gpio_context.gpio_hal, gpio_context.isr_core_id, &gpio_intr_status);
|
|
|
|
|
2018-12-21 09:07:51 -05:00
|
|
|
if (gpio_intr_status) {
|
|
|
|
gpio_isr_loop(gpio_intr_status, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
//read status1 to get interrupt status for GPIO32-39
|
2019-08-08 00:00:45 -04:00
|
|
|
uint32_t gpio_intr_status_h;
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_hal_get_intr_status_high(gpio_context.gpio_hal, gpio_context.isr_core_id, &gpio_intr_status_h);
|
|
|
|
|
2018-12-21 09:07:51 -05:00
|
|
|
if (gpio_intr_status_h) {
|
|
|
|
gpio_isr_loop(gpio_intr_status_h, 32);
|
|
|
|
}
|
2016-12-24 07:45:57 -05:00
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t gpio_install_isr_service(int intr_alloc_flags)
|
2016-12-24 07:45:57 -05:00
|
|
|
{
|
2019-07-15 02:44:15 -04:00
|
|
|
GPIO_CHECK(gpio_context.gpio_isr_func == NULL, "GPIO isr service already installed", ESP_ERR_INVALID_STATE);
|
|
|
|
esp_err_t ret;
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_context.gpio_isr_func = (gpio_isr_func_t *) calloc(GPIO_NUM_MAX, sizeof(gpio_isr_func_t));
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
if (gpio_context.gpio_isr_func == NULL) {
|
|
|
|
ret = ESP_ERR_NO_MEM;
|
|
|
|
} else {
|
|
|
|
ret = gpio_isr_register(gpio_intr_service, NULL, intr_alloc_flags, &gpio_context.gpio_isr_handle);
|
2016-12-24 07:45:57 -05:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
|
|
|
return ret;
|
2016-12-24 07:45:57 -05:00
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t gpio_isr_handler_add(gpio_num_t gpio_num, gpio_isr_t isr_handler, void *args)
|
2016-12-24 07:45:57 -05:00
|
|
|
{
|
2019-07-15 02:44:15 -04:00
|
|
|
GPIO_CHECK(gpio_context.gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE);
|
2016-12-24 07:45:57 -05:00
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
2016-12-24 07:45:57 -05:00
|
|
|
gpio_intr_disable(gpio_num);
|
2019-07-15 02:44:15 -04:00
|
|
|
if (gpio_context.gpio_isr_func) {
|
|
|
|
gpio_context.gpio_isr_func[gpio_num].fn = isr_handler;
|
|
|
|
gpio_context.gpio_isr_func[gpio_num].args = args;
|
2016-12-24 07:45:57 -05:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_intr_enable_on_core (gpio_num, esp_intr_get_cpu(gpio_context.gpio_isr_handle));
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2016-12-24 07:45:57 -05:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t gpio_isr_handler_remove(gpio_num_t gpio_num)
|
2016-12-24 07:45:57 -05:00
|
|
|
{
|
2019-07-15 02:44:15 -04:00
|
|
|
GPIO_CHECK(gpio_context.gpio_isr_func != NULL, "GPIO isr service is not installed, call gpio_install_isr_service() first", ESP_ERR_INVALID_STATE);
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_intr_disable(gpio_num);
|
|
|
|
if (gpio_context.gpio_isr_func) {
|
|
|
|
gpio_context.gpio_isr_func[gpio_num].fn = NULL;
|
|
|
|
gpio_context.gpio_isr_func[gpio_num].args = NULL;
|
2016-12-24 07:45:57 -05:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
return ESP_OK;
|
2016-12-24 07:45:57 -05:00
|
|
|
}
|
|
|
|
|
2019-07-16 05:33:30 -04:00
|
|
|
void gpio_uninstall_isr_service(void)
|
2016-12-24 07:45:57 -05:00
|
|
|
{
|
2021-11-16 23:07:00 -05:00
|
|
|
gpio_isr_func_t *gpio_isr_func_free = NULL;
|
|
|
|
gpio_isr_handle_t gpio_isr_handle_free = NULL;
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-07-15 02:44:15 -04:00
|
|
|
if (gpio_context.gpio_isr_func == NULL) {
|
2021-11-16 23:07:00 -05:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2016-12-24 07:45:57 -05:00
|
|
|
return;
|
|
|
|
}
|
2021-11-16 23:07:00 -05:00
|
|
|
gpio_isr_func_free = gpio_context.gpio_isr_func;
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_context.gpio_isr_func = NULL;
|
2021-11-16 23:07:00 -05:00
|
|
|
gpio_isr_handle_free = gpio_context.gpio_isr_handle;
|
|
|
|
gpio_context.gpio_isr_handle = NULL;
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_context.isr_core_id = GPIO_ISR_CORE_ID_UNINIT;
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2021-11-16 23:07:00 -05:00
|
|
|
esp_intr_free(gpio_isr_handle_free);
|
|
|
|
free(gpio_isr_func_free);
|
2016-12-24 07:45:57 -05:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2019-07-17 23:34:49 -04:00
|
|
|
static void gpio_isr_register_on_core_static(void *param)
|
|
|
|
{
|
|
|
|
gpio_isr_alloc_t *p = (gpio_isr_alloc_t *)param;
|
|
|
|
//We need to check the return value.
|
|
|
|
p->ret = esp_intr_alloc(p->source, p->intr_alloc_flags, p->fn, p->arg, p->handle);
|
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t gpio_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, gpio_isr_handle_t *handle)
|
2016-10-08 02:12:55 -04:00
|
|
|
{
|
2016-11-07 01:16:52 -05:00
|
|
|
GPIO_CHECK(fn, "GPIO ISR null", ESP_ERR_INVALID_ARG);
|
2019-07-17 23:34:49 -04:00
|
|
|
gpio_isr_alloc_t p;
|
|
|
|
p.source = ETS_GPIO_INTR_SOURCE;
|
|
|
|
p.intr_alloc_flags = intr_alloc_flags;
|
|
|
|
p.fn = fn;
|
|
|
|
p.arg = arg;
|
|
|
|
p.handle = handle;
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
if(gpio_context.isr_core_id == GPIO_ISR_CORE_ID_UNINIT) {
|
|
|
|
gpio_context.isr_core_id = xPortGetCoreID();
|
2019-07-17 23:34:49 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-08-15 03:05:59 -04:00
|
|
|
esp_err_t ret;
|
|
|
|
#if CONFIG_FREERTOS_UNICORE
|
|
|
|
gpio_isr_register_on_core_static(&p);
|
|
|
|
ret = ESP_OK;
|
|
|
|
#else /* CONFIG_FREERTOS_UNICORE */
|
2019-07-15 02:44:15 -04:00
|
|
|
ret = esp_ipc_call_blocking(gpio_context.isr_core_id, gpio_isr_register_on_core_static, (void *)&p);
|
2019-08-15 03:05:59 -04:00
|
|
|
#endif /* !CONFIG_FREERTOS_UNICORE */
|
2021-11-16 23:07:00 -05:00
|
|
|
if (ret != ESP_OK) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "esp_ipc_call_blocking failed (0x%x)", ret);
|
|
|
|
return ESP_ERR_NOT_FOUND;
|
|
|
|
}
|
|
|
|
if (p.ret != ESP_OK) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "esp_intr_alloc failed (0x%x)", p.ret);
|
2019-07-17 23:34:49 -04:00
|
|
|
return ESP_ERR_NOT_FOUND;
|
|
|
|
}
|
|
|
|
return ESP_OK;
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
|
|
|
|
{
|
2016-11-07 01:16:52 -05:00
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
2016-10-08 02:12:55 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2019-07-15 02:44:15 -04:00
|
|
|
|
|
|
|
if ((intr_type == GPIO_INTR_LOW_LEVEL) || (intr_type == GPIO_INTR_HIGH_LEVEL)) {
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_RTCIO_WAKE_SUPPORTED
|
2019-07-15 02:44:15 -04:00
|
|
|
if (rtc_gpio_is_valid_gpio(gpio_num)) {
|
2018-08-13 18:57:32 -04:00
|
|
|
ret = rtc_gpio_wakeup_enable(gpio_num, intr_type);
|
|
|
|
}
|
2021-02-05 04:10:44 -05:00
|
|
|
#endif
|
2020-04-27 08:30:23 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
2021-12-30 07:31:38 -05:00
|
|
|
gpio_hal_set_intr_type(gpio_context.gpio_hal, gpio_num, intr_type);
|
|
|
|
gpio_hal_wakeup_enable(gpio_context.gpio_hal, gpio_num);
|
2022-02-08 20:27:27 -05:00
|
|
|
#if SOC_GPIO_SUPPORT_SLP_SWITCH && CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
|
2021-03-11 06:25:54 -05:00
|
|
|
gpio_hal_sleep_sel_dis(gpio_context.gpio_hal, gpio_num);
|
|
|
|
#endif
|
2020-04-27 08:30:23 -04:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2016-10-08 02:12:55 -04:00
|
|
|
} else {
|
2018-08-13 18:57:32 -04:00
|
|
|
ESP_LOGE(GPIO_TAG, "GPIO wakeup only supports level mode, but edge mode set. gpio_num:%u", gpio_num);
|
2016-10-08 02:12:55 -04:00
|
|
|
ret = ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
2016-10-08 02:12:55 -04:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_wakeup_disable(gpio_num_t gpio_num)
|
|
|
|
{
|
2016-11-07 01:16:52 -05:00
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_RTCIO_WAKE_SUPPORTED
|
2019-07-15 02:44:15 -04:00
|
|
|
if (rtc_gpio_is_valid_gpio(gpio_num)) {
|
|
|
|
ret = rtc_gpio_wakeup_disable(gpio_num);
|
|
|
|
}
|
2021-02-05 04:10:44 -05:00
|
|
|
#endif
|
2020-04-27 08:30:23 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_wakeup_disable(gpio_context.gpio_hal, gpio_num);
|
2022-02-08 20:27:27 -05:00
|
|
|
#if SOC_GPIO_SUPPORT_SLP_SWITCH && CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
|
2021-04-08 23:35:32 -04:00
|
|
|
gpio_hal_sleep_sel_en(gpio_context.gpio_hal, gpio_num);
|
|
|
|
#endif
|
2020-04-27 08:30:23 -04:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-07-15 02:44:15 -04:00
|
|
|
return ret;
|
2016-10-08 02:12:55 -04:00
|
|
|
}
|
2017-07-17 03:38:19 -04:00
|
|
|
|
|
|
|
esp_err_t gpio_set_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t strength)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
GPIO_CHECK(strength < GPIO_DRIVE_CAP_MAX, "GPIO drive capability error", ESP_ERR_INVALID_ARG);
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
|
2020-09-09 22:37:58 -04:00
|
|
|
if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_set_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-11-26 07:00:24 -05:00
|
|
|
} else {
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
2019-11-26 07:00:24 -05:00
|
|
|
ret = rtc_gpio_set_drive_capability(gpio_num, strength);
|
2020-11-26 03:56:13 -05:00
|
|
|
#else
|
|
|
|
abort(); // This should be eliminated as unreachable, unless a programming error has occured
|
|
|
|
#endif
|
2017-07-17 03:38:19 -04:00
|
|
|
}
|
2019-11-26 07:00:24 -05:00
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
return ret;
|
2017-07-17 03:38:19 -04:00
|
|
|
}
|
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t gpio_get_drive_capability(gpio_num_t gpio_num, gpio_drive_cap_t *strength)
|
2017-07-17 03:38:19 -04:00
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
GPIO_CHECK(strength != NULL, "GPIO drive capability pointer error", ESP_ERR_INVALID_ARG);
|
2019-07-15 02:44:15 -04:00
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
|
2020-09-09 22:37:58 -04:00
|
|
|
if (!rtc_gpio_is_valid_gpio(gpio_num) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_get_drive_capability(gpio_context.gpio_hal, gpio_num, strength);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-11-26 07:00:24 -05:00
|
|
|
} else {
|
2020-11-26 03:56:13 -05:00
|
|
|
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
|
2019-11-26 07:00:24 -05:00
|
|
|
ret = rtc_gpio_get_drive_capability(gpio_num, strength);
|
2020-11-26 03:56:13 -05:00
|
|
|
#else
|
|
|
|
abort(); // This should be eliminated as unreachable, unless a programming error has occured
|
|
|
|
#endif
|
2017-07-17 03:38:19 -04:00
|
|
|
}
|
2019-11-26 07:00:24 -05:00
|
|
|
|
2019-07-15 02:44:15 -04:00
|
|
|
return ret;
|
2017-07-17 03:38:19 -04:00
|
|
|
}
|
2018-04-03 10:09:30 -04:00
|
|
|
|
|
|
|
esp_err_t gpio_hold_en(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED);
|
2019-07-15 02:44:15 -04:00
|
|
|
int ret = ESP_OK;
|
|
|
|
|
|
|
|
if (rtc_gpio_is_valid_gpio(gpio_num)) {
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_RTCIO_HOLD_SUPPORTED
|
2019-07-15 02:44:15 -04:00
|
|
|
ret = rtc_gpio_hold_en(gpio_num);
|
2021-02-05 04:10:44 -05:00
|
|
|
#endif
|
2019-06-13 03:37:58 -04:00
|
|
|
} else if (GPIO_HOLD_MASK[gpio_num]) {
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_hold_en(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2018-04-03 10:09:30 -04:00
|
|
|
} else {
|
2019-07-15 02:44:15 -04:00
|
|
|
ret = ESP_ERR_NOT_SUPPORTED;
|
2018-04-03 10:09:30 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
|
|
|
return ret;
|
2018-04-03 10:09:30 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_hold_dis(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "Only output-capable GPIO support this function", ESP_ERR_NOT_SUPPORTED);
|
2019-07-15 02:44:15 -04:00
|
|
|
int ret = ESP_OK;
|
|
|
|
|
|
|
|
if (rtc_gpio_is_valid_gpio(gpio_num)) {
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_RTCIO_HOLD_SUPPORTED
|
2019-07-15 02:44:15 -04:00
|
|
|
ret = rtc_gpio_hold_dis(gpio_num);
|
2021-02-05 04:10:44 -05:00
|
|
|
#endif
|
2019-06-13 03:37:58 -04:00
|
|
|
}else if (GPIO_HOLD_MASK[gpio_num]) {
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_hold_dis(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-06-13 03:37:58 -04:00
|
|
|
} else {
|
2019-07-15 02:44:15 -04:00
|
|
|
ret = ESP_ERR_NOT_SUPPORTED;
|
2019-06-13 03:37:58 -04:00
|
|
|
}
|
2019-07-15 02:44:15 -04:00
|
|
|
|
|
|
|
return ret;
|
2018-04-23 13:23:12 -04:00
|
|
|
}
|
|
|
|
|
2018-12-07 08:44:43 -05:00
|
|
|
void gpio_deep_sleep_hold_en(void)
|
|
|
|
{
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_deep_sleep_hold_en(gpio_context.gpio_hal);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2018-12-07 08:44:43 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
void gpio_deep_sleep_hold_dis(void)
|
|
|
|
{
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_deep_sleep_hold_dis(gpio_context.gpio_hal);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2018-12-07 08:44:43 -05:00
|
|
|
}
|
|
|
|
|
2020-09-09 22:37:58 -04:00
|
|
|
#if SOC_GPIO_SUPPORT_FORCE_HOLD
|
2019-06-13 03:37:58 -04:00
|
|
|
|
|
|
|
esp_err_t gpio_force_hold_all()
|
|
|
|
{
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_RTCIO_HOLD_SUPPORTED
|
2019-06-13 03:37:58 -04:00
|
|
|
rtc_gpio_force_hold_all();
|
2021-02-05 04:10:44 -05:00
|
|
|
#endif
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
2021-12-30 07:31:38 -05:00
|
|
|
gpio_hal_force_hold_all();
|
2019-07-15 02:44:15 -04:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-06-13 03:37:58 -04:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_force_unhold_all()
|
|
|
|
{
|
2021-02-05 04:10:44 -05:00
|
|
|
#if SOC_RTCIO_HOLD_SUPPORTED
|
2019-06-13 03:37:58 -04:00
|
|
|
rtc_gpio_force_hold_dis_all();
|
2021-02-05 04:10:44 -05:00
|
|
|
#endif
|
2019-07-15 02:44:15 -04:00
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
2021-02-05 04:10:44 -05:00
|
|
|
gpio_hal_force_unhold_all();
|
2019-07-15 02:44:15 -04:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
2019-06-13 03:37:58 -04:00
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-04-23 13:23:12 -04:00
|
|
|
void gpio_iomux_in(uint32_t gpio, uint32_t signal_idx)
|
|
|
|
{
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_hal_iomux_in(gpio_context.gpio_hal, gpio, signal_idx);
|
2018-04-23 13:23:12 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
void gpio_iomux_out(uint8_t gpio_num, int func, bool oen_inv)
|
|
|
|
{
|
2019-07-15 02:44:15 -04:00
|
|
|
gpio_hal_iomux_out(gpio_context.gpio_hal, gpio_num, func, (uint32_t)oen_inv);
|
2018-04-23 13:23:12 -04:00
|
|
|
}
|
2020-11-12 07:39:55 -05:00
|
|
|
|
|
|
|
#if SOC_GPIO_SUPPORT_SLP_SWITCH
|
|
|
|
static esp_err_t gpio_sleep_pullup_en(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_sleep_pullup_en(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t gpio_sleep_pullup_dis(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_sleep_pullup_dis(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t gpio_sleep_pulldown_en(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_sleep_pulldown_en(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t gpio_sleep_pulldown_dis(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_sleep_pulldown_dis(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t gpio_sleep_input_disable(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
gpio_hal_sleep_input_disable(gpio_context.gpio_hal, gpio_num);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t gpio_sleep_input_enable(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
gpio_hal_sleep_input_enable(gpio_context.gpio_hal, gpio_num);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t gpio_sleep_output_disable(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
gpio_hal_sleep_output_disable(gpio_context.gpio_hal, gpio_num);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static esp_err_t gpio_sleep_output_enable(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_OUTPUT_GPIO(gpio_num), "GPIO output gpio_num error", ESP_ERR_INVALID_ARG);
|
|
|
|
gpio_hal_sleep_output_enable(gpio_context.gpio_hal, gpio_num);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_sleep_set_direction(gpio_num_t gpio_num, gpio_mode_t mode)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
if ((GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) != true) && (mode & GPIO_MODE_DEF_OUTPUT)) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "io_num=%d can only be input", gpio_num);
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
|
|
|
|
if (mode & GPIO_MODE_DEF_INPUT) {
|
|
|
|
gpio_sleep_input_enable(gpio_num);
|
|
|
|
} else {
|
|
|
|
gpio_sleep_input_disable(gpio_num);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (mode & GPIO_MODE_DEF_OUTPUT) {
|
|
|
|
gpio_sleep_output_enable(gpio_num);
|
|
|
|
} else {
|
|
|
|
gpio_sleep_output_disable(gpio_num);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_sleep_set_pull_mode(gpio_num_t gpio_num, gpio_pull_mode_t pull)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
GPIO_CHECK(pull <= GPIO_FLOATING, "GPIO pull mode error", ESP_ERR_INVALID_ARG);
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
|
|
|
|
switch (pull) {
|
|
|
|
case GPIO_PULLUP_ONLY:
|
|
|
|
gpio_sleep_pulldown_dis(gpio_num);
|
|
|
|
gpio_sleep_pullup_en(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_PULLDOWN_ONLY:
|
|
|
|
gpio_sleep_pulldown_en(gpio_num);
|
|
|
|
gpio_sleep_pullup_dis(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_PULLUP_PULLDOWN:
|
|
|
|
gpio_sleep_pulldown_en(gpio_num);
|
|
|
|
gpio_sleep_pullup_en(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case GPIO_FLOATING:
|
|
|
|
gpio_sleep_pulldown_dis(gpio_num);
|
|
|
|
gpio_sleep_pullup_dis(gpio_num);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ESP_LOGE(GPIO_TAG, "Unknown pull up/down mode,gpio_num=%u,pull=%u", gpio_num, pull);
|
|
|
|
ret = ESP_ERR_INVALID_ARG;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_sleep_sel_en(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_sleep_sel_en(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_sleep_sel_dis(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_sleep_sel_dis(gpio_context.gpio_hal, gpio_num);
|
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
|
|
|
|
esp_err_t gpio_sleep_pupd_config_apply(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
gpio_hal_sleep_pupd_config_apply(gpio_context.gpio_hal, gpio_num);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_sleep_pupd_config_unapply(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
GPIO_CHECK(GPIO_IS_VALID_GPIO(gpio_num), "GPIO number error", ESP_ERR_INVALID_ARG);
|
|
|
|
gpio_hal_sleep_pupd_config_unapply(gpio_context.gpio_hal, gpio_num);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
2021-02-05 04:10:44 -05:00
|
|
|
#endif // CONFIG_GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL
|
|
|
|
#endif // SOC_GPIO_SUPPORT_SLP_SWITCH
|
|
|
|
|
|
|
|
#if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
|
|
|
|
esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t intr_type)
|
|
|
|
{
|
|
|
|
if (!gpio_hal_is_valid_deepsleep_wakeup_gpio(gpio_num)) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "GPIO %d does not support deep sleep wakeup", gpio_num);
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
if ((intr_type != GPIO_INTR_LOW_LEVEL) && (intr_type != GPIO_INTR_HIGH_LEVEL)) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "GPIO wakeup only supports level mode, but edge mode set. gpio_num:%u", gpio_num);
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_deepsleep_wakeup_enable(gpio_context.gpio_hal, gpio_num, intr_type);
|
2022-02-08 20:27:27 -05:00
|
|
|
#if SOC_GPIO_SUPPORT_SLP_SWITCH && CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
|
2021-04-08 23:35:32 -04:00
|
|
|
gpio_hal_sleep_sel_dis(gpio_context.gpio_hal, gpio_num);
|
|
|
|
#endif
|
2021-02-05 04:10:44 -05:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num)
|
|
|
|
{
|
|
|
|
if (!gpio_hal_is_valid_deepsleep_wakeup_gpio(gpio_num)) {
|
|
|
|
ESP_LOGE(GPIO_TAG, "GPIO %d does not support deep sleep wakeup", gpio_num);
|
|
|
|
return ESP_ERR_INVALID_ARG;
|
|
|
|
}
|
|
|
|
portENTER_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
gpio_hal_deepsleep_wakeup_disable(gpio_context.gpio_hal, gpio_num);
|
2022-02-08 20:27:27 -05:00
|
|
|
#if SOC_GPIO_SUPPORT_SLP_SWITCH && CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
|
2021-04-08 23:35:32 -04:00
|
|
|
gpio_hal_sleep_sel_en(gpio_context.gpio_hal, gpio_num);
|
|
|
|
#endif
|
2021-02-05 04:10:44 -05:00
|
|
|
portEXIT_CRITICAL(&gpio_context.gpio_spinlock);
|
|
|
|
return ESP_OK;
|
|
|
|
}
|
|
|
|
#endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
|